| Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
| ICD |
2005-04-14
09:00 |
Fukuoka |
|
A Read-Static-Noise-Margin-Free SRAM cell for low-Vdd and High-speed applications
Koichi Takeda, Yasuhiko Hagihara (NEC), Yoshiharu Aimoto (NECEL), Masahiro Nomura, Yoetsu Nakazawa (NEC), Toshio Ishii, Hiroyuki Kobatake (NECEL) |
A read-static-noise-margin-free SRAM cell consists of seven transistors, several of which are low-Vt NMOS transistors us... [more] |
ICD2005-1
pp.1-6 |
| ICD |
2005-04-14
09:30 |
Fukuoka |
|
Low-Power Embedded SRAM Modules with Expanded Margins for Writing
Masanao Yamaoka (Hitachi, Ltd.), Noriaki Maeda (Renesas), Yoshihiro Shinozaki (Hitachi ULSI), Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa (Renesas), Takayuki Kawahara (Hitachi, Ltd.) |
The power consumption of a low-power SoC has a battery life of mobile appliances. The general SoCs have large on-chip SR... [more] |
ICD2005-2
pp.7-12 |
| ICD |
2005-04-14
10:00 |
Fukuoka |
|
A 256Mb Synchronous Burst DDR SRAM using Single-crystal Silicon Thin Film Transisitor (SSTFT) SRAM cell
Youngho Suh, Hyouyoun Nam, Youngdae Lee, Hungiun An, Sangbeom Kang, Byunggil Choi, Hoon Lim, Choongkeun Kwak, Hyunguen Byun (Samsung) |
[more] |
ICD2005-3
pp.13-17 |
| ICD |
2005-04-14
10:40 |
Fukuoka |
|
[Invited Talk]
DRAM in the Nanoscale Era
-- Non-1T1C approaches --
Tomoyuki Ishii (Hitachi) |
Challenges for future DRAM technology in the nano-scale process generation are introduced. From operational stability p... [more] |
ICD2005-4
pp.19-22 |
| ICD |
2005-04-14
11:40 |
Fukuoka |
|
A 128Mb DRAM Using a 1T Gain Cell(FBC) on SOI
Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda (Toshiba), Tomoki Higashi (Toshiba Microelectronics), Mutsuo Morikado, Yoshihiro Minami, Tomoaki Shino, Hiroomi Nakajima, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe (Toshiba) |
We report on a 128Mbit DRAM design using the capacitor-less DRAM cell or the floating body cell(FBC) on SOI. The cell of... [more] |
ICD2005-5
pp.23-28 |
| ICD |
2005-04-14
13:00 |
Fukuoka |
|
[Invited Talk]
*
Hiroyuki Yamauchi (Matsushita) |
Based on the actual examples of where, how and why each memory is used, the representative embedded memories are classif... [more] |
ICD2005-6
pp.29-34 |
| ICD |
2005-04-14
14:00 |
Fukuoka |
|
A 196-mm2, 2-Gb DDR2 SDRAM using an 80-nm Triple Metal Technology
Jeong Hoon kook, Kyehyun Kyung, Chiwook Kim, Jaeyoung Lee (Samsung) |
[more] |
ICD2005-7
pp.35-36 |
| ICD |
2005-04-14
14:30 |
Fukuoka |
|
[Invited Talk]
Statistical Integration In Multigigabit DRAM Design
Tomonori Sekiguchi, Satoru Akiyama (Hitachi), Kazuhiko Kajigaya (Elpida), Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara (Hitachi) |
Concordant memory-array design incorporates device fluctuations statistically into signal-to-noise ratio analysis in DRA... [more] |
ICD2005-8
pp.37-42 |
| ICD |
2005-04-14
15:15 |
Fukuoka |
|
Improved write methods for 64Mb Phase-change Random Access Memory (PRAM)
Hyung-rok Oh, Beak-hyung Cho, Woo Yeong Cho, Sangbeom Kang, Byung-gil Choi, Hye-jin Kim, Ki-sung Kim, Du-eung Kim, Choong-keun Kwak, Hyun-geun Byun, Gi-tae Jeong, Hong-sik Jeong, Kinam Kim (Samsung) |
[more] |
ICD2005-9
pp.43-45 |
| ICD |
2005-04-14
15:45 |
Fukuoka |
|
A 146mm2 8Gb NAND Flash Memory with 70nm CMOS Technology
Takumi Abe, Takahiko Hara, Koichi Fukuda, Kazuhisa Kanazawa, Noboru Shibata, Koji Hosono, Hiroshi Maejima, Michio Nakagawa, Masatsugu Kojima, Masaki Fujiu, Yoshiaki Takeuchi, Kazumi Amemiya, Midori Morooka (Toshiba), Teruhiko Kamei, Hiroaki Nasu (SanDisk) |
[more] |
ICD2005-10
pp.47-52 |
| ICD |
2005-04-14
16:15 |
Fukuoka |
|
4Gb Multilevel AG-AND Flash Memory with 10MB/s Programming Throughput
Hideaki Kurata, Yoshitaka Sasago, Kazuo Otsuga, Tsuyoshi Arigane, Tetsufumi Kawamura, Takashi Kobayashi, Hitoshi Kume (Hitachi), Kazuki Homma, Kenji Kozakai, Satoshi Noda, Teruhiko Ito, Masahiro Shimizu, Yoshihiro Ikeda, Osamu Tsuchiya, Kazunori Furusawa (RENESAS) |
We fabricated a 4Gb multilevel AG-AND flash memory using 90nm CMOS technology. By using an inversion-layer local-bitline... [more] |
ICD2005-11
pp.53-58 |
| ICD |
2005-04-14
19:00 |
Fukuoka |
|
*
Katsuyuki Sato (Elpida), Hiroyuki Yamauchi (Matsushita), Kenji Numata (Toshiba), Takashi Akazawa (Renesas), Yasunao Katayama (IBM Japan) |
[more] |
ICD2005-12
p.59 |
| ICD |
2005-04-15
10:30 |
Fukuoka |
|
A 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture
Takaharu Tsuji (Renesas Technorogy), Hiroaki Tanizaki (Renesas Device Design), Masatoshi Ishikawa, Jun Otani, Yuichiro Yamaguchi, Shuichi Ueno, Tsukasa Oishi, Hideto Hidaka (Renesas Technorogy) |
A 1Mbit MRAM with a 0.81um2 1-Transistor 1-Magnetic Tunnel Junction (1T-1MTJ) cell using 0.13um 4LM logic technology has... [more] |
ICD2005-13
pp.1-6 |
| ICD |
2005-04-15
11:00 |
Fukuoka |
|
High Density and Low Power Nonvolatile FeRAM Memory Cell Architecture
Takashi Miki, Hiroshige Hirano, Masahiko Sakagami, Tetsuji Nakakuma, Kunisato Yamaoka, Shunichi Iwanari, Yasuo Murakuki, Yasushi Gohou, Eiji Fujii (Matsushita Electric Industrial Co., Ltd.) |
[more] |
ICD2005-14
pp.7-12 |
| ICD |
2005-04-15
11:30 |
Fukuoka |
|
Burst-Cycle Data Compression Schemes for Pre-Fuse Wafer-Level Test in Large Scale High-Speed embedded DRAM
Ryo Fukuda, Kenji Kobayashi (Toshiba Corp.), Masashi Akamatsu, Minoru Kaihatsu, Atsushi Tamura, Kazuo Taniguchi (Sony Corp.), Yohji Watanabe (Toshiba Corp.) |
This paper describes two novel data compression schemes suitable for high density and high speed embedded DRAMs. The par... [more] |
ICD2005-15
pp.13-17 |
| ICD |
2005-04-15
13:00 |
Fukuoka |
|
A 1.5-ns Access-Time 0.25-μm CMOS/SIMOX SRAM Macrocell
-- High Speed and Low-Power Operation by Using Dual-Wordline Scheme --
Nobutaro Shibata, Takako Ishihara (NTT), Shigehiro Kurita, Hideomi Okiyama (NEL) |
This paper presents high speed and low-power circuit techniques for small size SRAMs (e.g., on-chip cache memories). Rea... [more] |
ICD2005-16
pp.19-24 |
| ICD |
2005-04-15
13:30 |
Fukuoka |
|
Application of Bank-Based Multiport Memory to the Microprocessor Caches
Koh Johguchi, Zhaomin Zhu (Hiroshima Univ.), Tai Hirakawa (Hiroshima City Univ.), Hans Juergen Mattausch, Tetsushi Koide (Hiroshima Univ.), Tetsuo Hironaka, Kazuya Tanigawa (Hiroshima City Univ.) |
[more] |
ICD2005-17
pp.25-30 |
| ICD |
2005-04-15
14:00 |
Fukuoka |
|
Analysys of SRAM neutron-Induced Errors Based on the Consideration of Both Charge-Collection and Parasitic-BipolarFailure Modes
Kenichi Osada (Hitachi), Naoki Kitai (Hitachi ULSI), Shiro Kamohara (Renesas), Takayuki Kawahara (Hitachi) |
This paper describes an investigation of the upsetting of values in cells hit by alpha particles or neutrons, in which t... [more] |
ICD2005-18
pp.31-36 |
| ICD |
2005-04-15
14:30 |
Fukuoka |
|
New Development of Neutron-induced Soft-Error Simulation Technology
Taiki Uemura, Yoshiharu Tosaka, Yoshio Ashizawa, Hideki Oka, Shigeo Satoh (Fujitsu lab.) |
In these years, the interest in soft error becomes increasing. This comes from the problem that the soft error occurs no... [more] |
ICD2005-19
pp.37-42 |
|