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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, HWS, ICD | 2024-02-29 10:10 |
Okinawa | (Primary: On-site, Secondary: Online) |
()  VLD2023-108 HWS2023-68 ICD2023-97 |
(To be available after the conference date) [more] | VLD2023-108 HWS2023-68 ICD2023-97 pp.54-59 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-15 13:35 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
Loop optimization method for machine learning model in hardware-Trojan Detection Ryotaro Negishi, Nozomu Togawa (Waseda Univ.) VLD2023-31 ICD2023-39 DC2023-38 RECONF2023-34 |
(To be available after the conference date) [more] | VLD2023-31 ICD2023-39 DC2023-38 RECONF2023-34 pp.7-12 |
| SCE | 2023-08-08 14:25 |
Kanagawa | Yokohama National Univ. (Primary: On-site, Secondary: Online) |
In-Depth Timing Characterization of the Adiabatic Quantum-Flux-Parametron Logic Gate Yu Hoshika (YNU), Christopher L. Ayala (IAS- YNU), Nobuyuki Yoshikawa (IAS - YNU) SCE2023-9 |
Adiabatic quantum-flux-parametron (AQFP) logic is a superconductor logic family and can operate at 5 GHz to 10 GHz with ... [more] | SCE2023-9 pp.45-48 |
| HWS, VLD [detail] | 2020-03-06 15:20 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
NA Tomotaka Inoue, Kento Hasegawa, Nozomu Togawa (Waseda Univ.) VLD2019-133 HWS2019-106 |
NA [more] | VLD2019-133 HWS2019-106 pp.227-232 |
| SCE | 2019-01-23 13:30 |
Tokyo | Development of 30-GHz Datapath for Bit-Parallel, Gate-Level-Pipelined Rapid Single-Flux-Quantum Microprocessors Ikki Nagaoka (Nagoya Univ), Yuki Hatanaka (Mitsubishi Elec), Yuichi Matsui (Nagoya Univ), Koki Ishida (Kyushu Univ), Masamitsu Tanaka, Kyosuke Sano, Taro Yamashita (Nagoya Univ), Takatsugu Ono, Koji Inoue (Kyushu Univ), Akira Fujimaki (Nagoya Univ) SCE2018-30 |
We have started development of high-throughput single-flux-quantum (SFQ) microprocessors with the aim of higher throughp... [more] | SCE2018-30 pp.29-34 |
|
| CAS, SIP, MSS, VLD | 2018-06-15 16:25 |
Hokkaido | Hokkaido Univ. (Frontier Research in Applied Sciences Build.) | * Tomotaka Inoue, Kento Hasegawa (Waseda Univ.), Yuki Kobayashi (NEC), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) CAS2018-33 VLD2018-36 SIP2018-53 MSS2018-33 |
(To be available after the conference date) [more] | CAS2018-33 VLD2018-36 SIP2018-53 MSS2018-33 pp.173-178 |
| SCE | 2017-08-09 14:35 |
Aichi | Nagoya Univ. (Higashiyama Campus) | Design of Component Circuits for Rapid Single-Flux-Quantum Gate-Level-Pipelined Microprocessors Yuki Hatanaka, Yuichi Matsui, Masamitsu Tanaka, Kyosuke Sano, Akira Fujimaki (Nagoya Univ.), Koki Ishida, Takatsugu Ono, Koji Inoue (Kyushu Univ.) SCE2017-17 |
We have started development of high-throughput rapid single-flux-quantum (RSFQ) microprocessors with the aim of higher p... [more] | SCE2017-17 pp.37-42 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 10:10 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Quantitative Criterion of Gate-Level Netlist Vulnerability Masaru Oya, Youhua Shi (Waseda Univ.), Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo (NEC), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-59 DC2015-55 |
Recently, digital ICs are designed by outside vendors to reduce costs in semiconductor industry. This circumstance intr... [more] |
VLD2015-59 DC2015-55 pp.141-146 |
| VLD | 2015-03-04 10:20 |
Okinawa | Okinawa Seinen Kaikan | Optimization of sequential circuit in gate-level pipelined self-synchronous circuit design Atsushi Ito, Makoto Ikeda (The Univ. of Tokyo) VLD2014-177 |
With the down-scaling, circuit which has higher robustness is demanded. Dual-pipeline self synchronous circuit have inhe... [more] | VLD2014-177 pp.135-140 |
| VLD | 2015-03-04 13:25 |
Okinawa | Okinawa Seinen Kaikan | A Score-Based Hardware-Trojan Identification Method for Gate-Level Netlists Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-182 |
Recently, digital ICs are designed by outside vendors to reduce costs in semiconductor industry. This circumstance intr... [more] |
VLD2014-182 pp.165-170 |
| RECONF, CPSY, VLD, IPSJ-SLDM [detail] | 2015-01-30 10:50 |
Kanagawa | Hiyoshi Campus, Keio University | A Hardware Trojan Detection Method based on Trojan net features Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-137 CPSY2014-146 RECONF2014-70 |
Recently, digital ICs are designed by outside vendors to reduce costs in semiconductor industry. This circumstance intr... [more] |
VLD2014-137 CPSY2014-146 RECONF2014-70 pp.157-162 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 17:30 |
Oita | B-ConPlaza | A Hardware Trojans Detection Method focusing on Nets in Hardware Trojans in Gate-Level Netlists Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-91 DC2014-45 |
Recently, digital ICs are designed by outside vendors to reduce design costs in semiconductor industry. This circumstan... [more] |
VLD2014-91 DC2014-45 pp.135-140 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 10:05 |
Oita | B-ConPlaza | Optimization for gate-level pipelined self-synchrnous circuit Atsushi Ito, Makoto Ikeda (Univ. of Tokyo) VLD2014-107 DC2014-61 |
With the down-scaling, circuit which has higher robustness is demanded. Dual-pipeline self synchronous circuit have inhe... [more] | VLD2014-107 DC2014-61 pp.233-238 |
| VLD | 2011-03-04 13:10 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | An evaluation of error detection/correction circuits by gate level simulation Masafumi Inoue (Tokyo Tech.), Yuuta Ukon, Atsushi Takahashi (Osaka Univ.) VLD2010-141 |
In a typical synchronous circuit design, the maximum delay between flip-flops gives a lower bound of the clock period su... [more] | VLD2010-141 pp.147-152 |
| VLD, CAS, SIP | 2008-06-27 09:40 |
Hokkaido | Hokkaido Univ. | An Approach to RTL-GL Path Mapping Based on Functional Equivalence Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara (NAIST) CAS2008-21 VLD2008-34 SIP2008-55 |
Information on false paths in a circuit is useful for design and test. The use of this information may contribute not o... [more] | CAS2008-21 VLD2008-34 SIP2008-55 pp.13-18 |
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