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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-25 14:50 |
Online | Online | Efficient Attention Mechanism by Softmax Function with Trained Coefficient Kaito Hirota (UT), O'uchi Shinichi (AIST), Fujita Masahiro (UT)  VLD2020-48 CPSY2020-31 RECONF2020-67 |
BERT is a neural network model which has accomplished state-of-the-art performance on eleven natural language processing... [more] | VLD2020-48 CPSY2020-31 RECONF2020-67 pp.52-57 |
| RECONF | 2016-05-19 16:15 |
Kanagawa | FUJITSU LAB. | Checkpointing and Live-Migration on FPGA-based Supercomputing Shinya Takamaeda, Vu Hoang Gia, Supasit Kajkamhaeng (NAIST) RECONF2016-13 |
(To be available after the conference date) [more] | RECONF2016-13 pp.61-66 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-21 15:45 |
Kanagawa | Hiyoshi Campus, Keio University | Search of Evaluation Function with Genetic Algorithm and UML Model-based Development for TRAX Player Ryo Tamaki, Naohiko Shimizu (Tokai Univ.) VLD2015-110 CPSY2015-142 RECONF2015-92 |
In this paper, We present the game tree search and the hardware design for the TRAX player. The TRAX player searches the... [more] | VLD2015-110 CPSY2015-142 RECONF2015-92 pp.237-242 |
| RECONF | 2015-09-18 13:00 |
Ehime | Ehime University | A High-level Hardware Design Environment in Python Shinya Takamaeda (NAIST) RECONF2015-36 |
In software development, on standard computers, there are numerous alternatives of programming languages. In contrast, t... [more] | RECONF2015-36 pp.21-26 |
| RCS | 2014-06-17 10:05 |
Okinawa | Okinawa-ken Seinenkaikan (Naha) | A Design of MIMO Decoder using LLR Approximation without Maximum Value Calculation Reina Hongyo, Thi Hong Tran, Hiroshi Ochi (Kyusyu Inst. of Tech.) RCS2014-39 |
In Multiple Input Multiple Output (MIMO) decoders, soft decision bits in the form of Log Likelihood Ratio (LLR) are ofte... [more] | RCS2014-39 pp.43-48 |
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-17 13:50 |
Kanagawa | The method for automation of design verification using UML diagram Daiki Kano (Tokai Univ.), Naohiko Shimizu (Tokai Univ./IP ARCH, Inc.) VLD2012-131 CPSY2012-80 RECONF2012-85 |
We develop the method for hardware design using UML diagram, in order to develop the hardware efficiently.We propose the... [more] | VLD2012-131 CPSY2012-80 RECONF2012-85 pp.141-146 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 13:50 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | The Attempt to Model-Based Hardware Development Using SysML Ryota Yamazaki (Tokai Univ), Naohiko Shimizu (Tokai Univ/IP ARCH Inc.) RECONF2012-58 |
In this paper, we analyze the system of the MP3 encoder using SysML, and show the example of the system model. and, We ... [more] | RECONF2012-58 pp.63-69 |
| RECONF | 2011-09-26 14:20 |
Aichi | Nagoya Univ. | Development Modeling Compiler and Operation Test for the Hardware Design Generate HDL from UML State Machine Diagram Daiki Kano, Ryota Yamazaki (Tokai Univ.), Naohiko Shimizu (Tokai Univ./IP ARCH, Inc.) RECONF2011-27 |
This paper describes the UML modeling compiler and operation test using that．The UML modeling compiler performs automati... [more] | RECONF2011-27 pp.31-36 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-30 13:15 |
Fukuoka | Kyushu University | A case study of the effective value range analysis for Behavioral synthesis Kenji Tomonaga, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2010-32 |
The digital circuit becomes more complex and larger scale recently, and behavioral synthesis that use behavioral descri... [more] |
CPSY2010-32 pp.1-6 |
| IT, ISEC, WBS | 2010-03-05 13:25 |
Nagano | Nagano-Engineering Campus, Shinshu University | Behavior Level Design of Turbo TCM Decoder
-- Automatic Synthesis of Pipeline Processing Circuit and Comparison of RTL Design -- Hayato Taira, Haruo Ogiwara (Nagaoka Univ. of Tech.) IT2009-122 ISEC2009-130 WBS2009-101 |
This paper shows a turbo TCM (Trellis Coded Modulation) hardware decoder design with a pipeline processing circuit using... [more] | IT2009-122 ISEC2009-130 WBS2009-101 pp.331-335 |
| SIP, CAS, CS | 2007-03-06 09:30 |
Tottori | Blancart Misasa (Tottori) | [Poster Presentation]
Cost Optimization Using Tabu Search in Hardware Design of Arbitrary Functions Koji Kotani, Takao Sasaki, Hisamichi Toyoshima (Kanagawa Univ.) CAS2006-95 SIP2006-196 CS2006-112 |
In digital circuit design using a hardware description language, some elementary functions and user defined functions ca... [more] | CAS2006-95 SIP2006-196 CS2006-112 pp.15-18 |
| NS, OCS (Joint) |
2007-01-26 13:00 |
Miyazaki | A Study on Buffer Control Mechanism Guaranteeing Various Delay-Bandwidth Requirements in Broadband Router Hideki Tode, Rie Fujita, Yusuke Shinohara, Koso Murakami (Osaka Univ.) NS2006-154 |
In this paper, to provide the enhanced QoS for various applications, we extensively propose new QoS control mechanism b... [more] |
NS2006-154 pp.19-24 |
|
| PN, NS (Joint) |
2006-12-15 10:55 |
Aichi | Nagoya Univ. | [Encouragement Talk]
Hardware-oriented Flow Managed Buffer Control Mechanism Yusuke Shinohara, Hideki Tode, Koso Murakami (Osaka Univ.) NS2006-144 |
Today’s IP network has trouble realizing QoS guarantee for each flow because the Best-Effort service is provided mainly... [more] |
NS2006-144 pp.29-34 |
| NS | 2006-06-23 11:15 |
Iwate | Iwate Prefectural University | Flow-Managed Packet Discarding Scheme Suitable for Broadband Routers Yusuke Shinohara, Norio Yamagaki, Hideki Tode, Koso Murakami (Osaka Univ.) NS2006-43 |
In today's IP network, the Best-Effort service is provided mainly. However, it has trouble realizing QoS guarantee for e... [more] | NS2006-43 pp.29-32 |
| NS, CS, IN | 2004-09-02 13:00 |
Miyagi | Tohoku University | -
-- - -- Norio Yamagaki, Hideki Tode, Koso Murakami (Osaka Univ.) |
Recently, various types of traffic have increased with the development of broadband networks. Thus, the realization of Q... [more] | NS2004-84 IN2004-43 CS2004-39 pp.1-4 |
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