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Committee Date Time Place Paper Title / Authors Abstract Paper #
NLP 2017-05-11
11:25		 Okayama Okayama University of Science Delta Sigma Domain LDPC Decoder Based on Min-Sum Algorithm
Akiyoshi Yasuda, Hisato Fujisaka, Masaru Fukushima, Takeshi Kamio (Hiroshima City Univ.) NLP2017-5		 Combination of interleaving and random error correction code is effective as a measure against burst error when power li... [more] NLP2017-5
pp.23-27
IT 2010-09-22
11:20		 Miyagi Tohoku Gakuin University A Sorting-Based Architecture of Finding the First Two Minimum Values
Qian Xie, Zhixiang Chen, Satoshi Goto (Waseda Univ.) IT2010-43		 In this paper we propose a sorting-based architecture of finding the first two minimum values. Given a set of numbers X,... [more] IT2010-43
pp.57-61
IT 2009-09-29
14:00		 Tokyo Sophia Univ. Implementation of LDPC decoder for 802.16e
Xiao Peng, Xiongxin Zhao, Zhixiang Chen, Satoshi Goto (Waseda Univ.) IT2009-34		 The implementation complexity of the decoder for Low-density Parity-check Codes (LDPC) is dictated by memory and interco... [more] IT2009-34
pp.9-12
IT 2008-09-11
17:55		 Okinawa Culture Resort Festone (Okinawa) Complexity-reducing Algorithm for Serial Min-sum Decoding
Hironori Uchikawa, Kohsuke Harada, Yasuhiko Tanabe (Toshiba) IT2008-28		 We propose a complexity-reducing algorithm for serial min-sum
decoding that reduces the number of check nodes to proce... [more]		 IT2008-28
pp.49-54
VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC
(Joint) [detail]		 2007-11-22
14:55		 Fukuoka Kitakyushu International Conference Center An LDPC Decoder Based on the Min-Sum Algorithm for High Speed WLAN Systems
Nozomu Hama, Hiroyuki Shimajiri, Takeo Yoshida (Univ. of the Ryukyus) VLD2007-100 DC2007-55		 In this paper, we show an architecture of low density parity check (LDPC) decoders based on the Min-Sum algorithm for hi... [more] VLD2007-100 DC2007-55
pp.67-72
ICD, ITE-CE 2006-01-27
14:15		 Tokyo Kikai-Shinko-Kaikan Bldg. High-Throughput LDPC Decoder Based on Memory-Reduction Method
Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto (Waseda Univ.) 		In this paper, we propose a high-throughput partially-parallel LDPC decoder for long code-length.
The decoder achieves... [more]		 ICD2005-220
pp.29-34
CAS, SIP, VLD 2005-06-28
14:15		 Miyagi Tohoku University A Memory-Reduction Method for Partially-Parallel LDPC Decoder Based on Min-Sum Algorithm
Tatsuyuki Ishikawa, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto (Waseda Univ.) 		In this paper, we propose a memory-reduction method for partially-parallel LDPC decoder based on min-sum algorithm. We ... [more] CAS2005-22 VLD2005-33 SIP2005-46
pp.43-48
 Results 1 - 7 of 7  /   
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