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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| NLP, MSS | 2024-03-14 16:05 |
Misc. | Kikai-Shinko-Kaikan Bldg. | Functional electrical stimulator with wireless sequential logic central pattern generator model Rikuto Nozu, Hiroyuki Torikai (Hosei Univ)  MSS2023-97 NLP2023-149 |
In this study, we design a functional electrical stimulator using a wireless sequential logic circuit central pattern ge... [more] | MSS2023-97 NLP2023-149 p.123 |
| QIT (2nd) |
2022-12-08 14:00 |
Kanagawa | Keio Univ. (Primary: On-site, Secondary: Online) |
[Poster Presentation]
Application of Sequential minimal Optimization Methods to UCCSD ansatz Yuichiro Tashima (Osaka Univ.), Kosuke Ito, Hideaki Hakoshima (Osaka Univ. QIQB), Kosuke Mitarai, Keisuke Fujii (Osaka Univ.) |
Variational quantum eigensolver (VQE) is expected to be applied to quantum chemical calculations. This algorithm uses p... [more] |
|
| HWS, VLD [detail] | 2020-03-06 13:00 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
Fundamental Study on Fault Analysis with Non-Uniform Faulty Values Caused at Fault Injection into Sequential Circuit Takumi Okamoto, Daisuke Fujimoto (NAIST), Kazuo Sakiyama, Li Yang (UEC), Yu-ichi Hayashi (NAIST) VLD2019-128 HWS2019-101 |
Fault analysis for the cryptographic module is roughly divided into two phases; those are injecting transient faults and... [more] | VLD2019-128 HWS2019-101 pp.197-201 |
| SCE | 2020-01-17 13:15 |
Kanagawa | [Poster Presentation]
Methodology for Automating Data Feedback Circuit Synthesis for a 4- bit Counter in Adiabatic Quantum-Flux-Parametron Logic Ro Saito (YNU), Christopher L. Ayala, Olivia Chen (YNU IAS), Tomoyuki Tanaka, Tomohiro Tamura, Nobuyuki Yoshikawa (YNU) SCE2019-58 |
Adiabatic quantum-flux-parametron (AQFP) logic is one kind of superconducting logic family spotlighted as a technologica... [more] | SCE2019-58 pp.117-119 |
|
| DC | 2018-02-20 11:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A test generation method based on k-cycle testing for finite state machines Yuya Kinoshita, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2017-81 |
Recent advances in semiconductor technologies have resulted in VLSI circuit density and complexity. As a result, efficie... [more] | DC2017-81 pp.25-30 |
| DC | 2017-02-21 14:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An Untestable Fault Identification Method for Sequential Circuits Based on SAT Using Unreachable States Morito Niseki, Toshinori Hosokawa (Nihon Univ.), Msayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) DC2016-79 |
Scan design has problems such as large hardware overhead and long test application time. Non-scan based test generation ... [more] | DC2016-79 pp.29-34 |
| DC | 2016-06-20 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Binding Method for Testability to Generate Easily Testable Functional Time Expansion Models Mamoru Sato, Toshinori hosokawa, Tetsuya Masuda, Jun Nishimaki (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2016-14 |
A test generation method for datapaths using easily testable functional time expansion models was proposed as efficient ... [more] | DC2016-14 pp.25-30 |
| NLP | 2016-03-24 13:25 |
Kyoto | Kyoto Sangyo Univ. | Implementation of Boltzmann Machine by Asynchronous Network of Cellular Automaton-based Neurons Takashi Matsubara, Kuniaki Uehara (Kove Univ.) NLP2015-143 |
Artificial neural networks with stochastic state transitions, such as Deep Boltzmann Machine, have excelled other machin... [more] | NLP2015-143 pp.7-10 |
| VLD, IPSJ-SLDM | 2015-05-14 11:35 |
Fukuoka | Kitakyushu International Conference Center | Control Signal Extraction for Sequential Clock Gating Using Time Expansion of Sequential Circuits Tomoya Goto, Kohei Higuchi, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2015-4 |
Recently, clock gating is utilized as a method for reducing the dynamic power of LSI. Clock gating can be automatically... [more] |
VLD2015-4 pp.31-36 |
| MW (2nd) |
2014-11-26 - 2014-11-28 |
Overseas | King Mongkut's Institute of Technology Ladkrabang (KMITL), Bangkok | Proposal of Sequentially Switched Antenna Array Receiver on High Speed Vehicles Entrance Satoru Aikawa, Ryosuke Baba, Shinichiro Yamamoto (Univ. of Hyogo), Satoshi Tsukamoto, Julian Webber, Masayuki Ariyoshi (ATR) |
The traffics from many smartphones in a bullet train are increasing. In this case, it is desirable to multiplex the traf... [more] | |
| MW (2nd) |
2014-11-26 - 2014-11-28 |
Overseas | King Mongkut's Institute of Technology Ladkrabang (KMITL), Bangkok | A Study of Combine Effect to Multiple Elements in Sequentially Switched Antenna Array Receiver Ryosuke Baba, Shinichiro Yamamoto, Satoru Aikawa (Univ. of Hyogo), Satoshi Tsukamoto, Julian Webber, Masayuki Ariyoshi (ATR) |
The traffics from many smartphones in a bullet train are increasing and fear the capacity lack of entrance circuit. In S... [more] | |
| CS | 2014-11-07 11:00 |
Hokkaido | Shiretoko (Hokkaido) | Combine Scheme to Multiple Elements in Sequentiqally Switched Antenna Array Receiver Ryosuke Baba, Shinichiro Yamamoto, Satoru Aikawa (Univ. of Hyogo), Satoshi Tsukamoto, Julian Webber, Masayuki Ariyoshi (ATR) CS2014-72 |
In recent years, mobile communication terminals such as smartphone are necessities of life, a number of terminals are pr... [more] | CS2014-72 pp.111-115 |
| DC | 2014-06-20 16:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An evaluation for Testability of Functional k-Time Expansion Models Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2014-17 |
A test generation method using functional k-time expansion models for data paths was proposed. In the test generation m... [more] |
DC2014-17 pp.45-50 |
| DC | 2013-06-21 13:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Controller Augmentation Method to Generate Functional k-Time Expansion Models for Data Path Circuits Yusuke Kodama, Jun Nishimaki, Tetsuya Masuda, Toshinori Hosokawa (Nihon Univ), Hideo Fujiwara (Osaka Gakuin Univ) DC2013-10 |
In recent years, various high-level test synthesis methods for LSIs have been proposed for the improvement in design pro... [more] | DC2013-10 pp.1-6 |
| NLP | 2012-01-24 09:45 |
Fukushima | Aizu-keiko-do Hall | An Asynchronous Sequential Logic Inner Hair Cell Model and its Response Characteristics Hironori Ishimoto, Hiroyuki Torikai (Osaka Univ.) NLP2011-135 |
In the mammalian inner ear, the basilar membrane vibrates in response to a sound wave and the inner hair cells transform... [more] | NLP2011-135 pp.63-68 |
| DC, CPSY | 2011-04-12 13:00 |
Tokyo | An Approach and Evaluation of Fault Tolerant Sequential Circuits for Simultaneous Occurrence of Multiple Transient Faults Satoshi Fukumoto, Kenta Imai, Hideo Kohinata, Masayuki Arai (Tokyo Metropolitan Univ.) CPSY2011-1 DC2011-1 |
This paper discusses the extension of highly reliable technique for sequential circuits using duplicate register which h... [more] | CPSY2011-1 DC2011-1 pp.1-4 |
|
| DC | 2011-02-14 14:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Test Generation Method for Datapath Circuits Using Functional Time Expansion Models Teppei Hayakawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) DC2010-65 |
Some large-scale integrated circuits have been recently designed at high-level by behavioral descriptions. Behavioral sy... [more] | DC2010-65 pp.39-44 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-12-01 11:25 |
Fukuoka | Kyushu University | A Sequential Test Generation Method and a Binding Method for Testability Using Behavioral Description Ryoichi Inoue, Hiroaki Fujiwara, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (NAIST) VLD2010-76 DC2010-43 |
Although many works on test generation algorithms for sequential circuits have been reported so far, it is still very ha... [more] | VLD2010-76 DC2010-43 pp.143-148 |
| VLD, IPSJ-SLDM | 2010-05-19 16:10 |
Fukuoka | Kitakyushu International Conference Center | Highly Accurate Approximate Methods for Soft Error Tolerance Estimation for Sequential Circuits Naoki Shirobayashi, Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) VLD2010-2 |
Soft error tolerance estimation method is necessary for soft error aware logic designs. There is an exact method has b... [more] |
VLD2010-2 pp.25-30 |
| VLD, IPSJ-SLDM | 2010-05-19 16:35 |
Fukuoka | Kitakyushu International Conference Center | An Approximate Method for Steady State Probability Calculation based on FSM Splitting So Hasegawa, Yusuke Akamine, Masayoshi Yoshimura, Yusuke Matsunaga (Kyushu Univ.) VLD2010-3 |
An exact method evaluate soft error tolerance with Markov model has been proposed. This method, however, is difficult t... [more] |
VLD2010-3 pp.31-36 |
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