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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2012-02-13 11:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Pattern Merging for Additional Path Delay Fault Detection with Transition Delay Fault Test Hiroaki Tanaka, Kohei Miyase, Kazunari Enokimoto, Xiaoqing Wen, Seiji Kajihara (Kyutech)  DC2011-78 |
In this paper, we present to generate a test vector set to detect both transition and path delay faults. The proposed me... [more] | DC2011-78 pp.13-18 |
| DC | 2011-06-24 16:20 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Low Power At-Speed Scan Testing for LOS Scheme by Test Vector Modification Kohei Miyase, Yuta Uchinodan, Kazunari Enokimoto (KIT), Yuta Yamato (NAIST), Xiaoqing Wen, Seiji Kajihara (KIT), Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Verazel (Lirmm) DC2011-13 |
In this paper, we present a test vector modification method to reduce launch-to-capture power for LOS scheme. The propos... [more] | DC2011-13 pp.29-34 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-03 14:05 |
Kochi | Kochi City Culture-Plaza | Optimizing Don't-Care Bit Rate Derived from X-Identification for Reduction of Switching Activity Isao Beppu (Kyushu Institute of Tech), Kohei Miyase (Kyushu Institute of Tech/JST), Yuta Yamato (Kyushu Institute of Tech), Xiaoqing Wen, Seiji Kajihara (Kyushu Institute of Tech/JST) VLD2009-55 DC2009-42 |
Increase of power dissipation and IR-drop during scan-shifting operation and/or capture operation is still challenging p... [more] | VLD2009-55 DC2009-42 pp.95-100 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 13:50 |
Fukuoka | Kitakyushu Science and Research Park | A Capture-Safe Test Generation Scheme for At-speed Scan Testing Atsushi Takashima, Yuta Yamato, Hiroshi Furukawa, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyusyu Institute of Technology) VLD2008-62 DC2008-30 |
Capture-safety, defined as the avoidance of any timing error due to unduly high switching activity in capture mode durin... [more] | VLD2008-62 DC2008-30 pp.13-18 |
| VLD, CPSY, RECONF, DC, IPSJ-SLDM, IPSJ-ARC (Joint) [detail] |
2007-11-20 10:30 |
Fukuoka | Kitakyushu International Conference Center | A Transition Delay Test Generation Method for Capture Power Reduction during At-Speed Scan Testing Tomoaki Fukuzawa, Kohei Miyase, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara (KIT) VLD2007-71 DC2007-26 |
High power dissipation can occur when a response to the test vector is captured by flip-flops in at-speed scan testing, ... [more] | VLD2007-71 DC2007-26 pp.7-12 |
| ICD, CPM | 2007-01-19 13:00 |
Tokyo | Kika-Shinko-Kaikan Bldg. | A Constrained Test Generation Method for Low Power Testing Yoshiaki Tounoue, Xiaoqing Wen, Seiji Kajihara (K I T), Kohei Miyase (JST), Tatsuya Suzuki, Yuta Yamato (K I T) |
High Power dissipation when the response to a test vector is captured by flip-flops in scan testing which may cause exce... [more] | CPM2006-148 ICD2006-190 pp.109-114 |
| VLD, ICD, DC, IPSJ-SLDM | 2005-12-02 09:30 |
Fukuoka | Kitakyushu International Conference Center | On Low Capture Power Test Generation for Scan Testing Tatsuya Suzuki, Xiaoqing Wen, Seiji Kajihara (K.I.T.), Kohei Miyase, Yoshihiro Minamoto (JST) |
High switching activity occurs when the response to a test vector is captured by flip-flops during scan testing. This ma... [more] | VLD2005-76 ICD2005-171 DC2005-53 pp.1-6 |
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