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Technical Committee on Integrated Circuits and Devices (ICD) (Searched in: 2018)
Search Results: Keywords 'from:2018-12-05 to:2018-12-05'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 10:55 |
Hiroshima | Satellite Campus Hiroshima | On the Generation of Random Capture Safe Test Vectors Using Neural Networks Sayuri Ochi, Kenichirou Misawa, Toshinori Hosokawa, Yukari Yamauchi, Masayuki Arai (Nihon Univ.)  VLD2018-51 DC2018-37 |
Excessive capture power consumption at scan testing causes the excessive IR drop and it might cause test-induced yield l... [more] | VLD2018-51 DC2018-37 pp.89-94 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 11:20 |
Hiroshima | Satellite Campus Hiroshima | Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2018-52 DC2018-38 |
(To be available after the conference date) [more] | VLD2018-52 DC2018-38 pp.95-100 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 10:30 |
Hiroshima | Satellite Campus Hiroshima | A Case Study on Memory Architecture Exploration for FPGA-based Manycores Seiya Shirakuni (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-53 DC2018-39 |
In the design of high-performance embedded systems, FPGA-based manycores attract an increasing attention. In embedded sy... [more] | VLD2018-53 DC2018-39 pp.101-106 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 10:55 |
Hiroshima | Satellite Campus Hiroshima | Improved Thread Execution for GPU-oriented OpenCL Programs on Multicore Processors Takafumi Miyazaki, Hayato Hidari, Naohisa Hojo (Ritsumeikan Univ), Naohisa Hojo (Osaka Univ), Hiroyuki Tomiyama (Ritsumeikan Univ) VLD2018-54 DC2018-40 |
[more] | VLD2018-54 DC2018-40 pp.107-111 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 11:20 |
Hiroshima | Satellite Campus Hiroshima | An FPGA-NIC Based 40-Gbit/s Automated Response Circuit for Invalid DNS Packets to Suppress CPU Utilization of DNS Content Server Shoko Ohteru, Saki Hatta, Tomoaki Kawamura (NTT), Koji Yamazaki (NTT-AT), Takahiro Hatano, Akihiko Miyazaki, Koyo Nitta (NTT) VLD2018-55 DC2018-41 |
(To be available after the conference date) [more] | VLD2018-55 DC2018-41 pp.113-118 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 13:00 |
Hiroshima | Satellite Campus Hiroshima | [Invited Talk]
What I should do beside dedicated AI hardwares Yasuhiko Nakashima (NAIST) CPSY2018-37 |
(To be available after the conference date) [more] | CPSY2018-37 pp.3-8 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 13:00 |
Hiroshima | Satellite Campus Hiroshima | Test Time Reduction by Separating Delay Lines in Boundary Scan Circuit with Embedded TDC Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2018-56 DC2018-42 |
3D die-stacking technique using TSVs has gained much attention as a new integration method of IC. However, faulty TSVs ... [more] |
VLD2018-56 DC2018-42 pp.119-124 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 13:25 |
Hiroshima | Satellite Campus Hiroshima | Evaluation of Flexible Test Power Control for Logic BIST in TEG Chips Takaaki Kato (KIT), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (KIT) VLD2018-57 DC2018-43 |
Scan-based logic BIST has a crucial problem of high test power dissipation. Its solution requires a flexible test power ... [more] | VLD2018-57 DC2018-43 pp.125-130 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 13:50 |
Hiroshima | Satellite Campus Hiroshima | Study on the Applicability of ATPG Pattern for DFT Circuit Kohki Taniguchi, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2018-58 DC2018-44 |
With high integration of IC, small delay faults have occurred as the cause of a circuit failure. As a design-for-testabi... [more] | VLD2018-58 DC2018-44 pp.131-136 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 14:15 |
Hiroshima | Satellite Campus Hiroshima | Register-Transfer Level Exploration of Segments Utilizable for Scan Path Synthesis Sho Yuasa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2018-59 DC2018-45 |
[more] | VLD2018-59 DC2018-45 pp.137-142 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 13:00 |
Hiroshima | Satellite Campus Hiroshima | An efficient SAT-attack algorithm against logic encryption Yusuke Matsunaga (Kyushu Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) VLD2018-60 DC2018-46 |
[more] | VLD2018-60 DC2018-46 pp.143-148 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 13:25 |
Hiroshima | Satellite Campus Hiroshima | A Hybrid Method Using Monte-Carlo Tree Search and Gibbs Sampling Method for Solving Motif Extraction Problems Yusuke Yuasa, Shinobu Nagayama, Masato Inagi, Shin'ichi Wakabayashi (HCU) VLD2018-61 DC2018-47 |
[more] | VLD2018-61 DC2018-47 pp.149-154 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 13:50 |
Hiroshima | Satellite Campus Hiroshima | Hiroki Nishimoto, Takashi Nakada, Yasuhiko Nakashima (NAIST) VLD2018-62 DC2018-48 |
[more] | VLD2018-62 DC2018-48 pp.155-160 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 14:00 |
Hiroshima | Satellite Campus Hiroshima | Triple modular redundancy optically reconfigurable gate array Toru Yoshinaga, Minoru Watanabe (Shizuoka Univ.) RECONF2018-43 |
[more] | RECONF2018-43 pp.51-54 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 14:25 |
Hiroshima | Satellite Campus Hiroshima | FPGA implementation of a robot control algorithm Yusuke Takaki, Minoru Watanabe (Shizuoka Univ.), Kentaro Sano (Riken) RECONF2018-44 |
[more] | RECONF2018-44 pp.55-60 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 14:55 |
Hiroshima | Satellite Campus Hiroshima | Design guideline of ground structure in slow wave transmission line Tomohiro Kobayashi, Syuhei Amakawa, Takeshi Yoshida, Minoru Fujishima (Hiroshima Univ) CPM2018-88 ICD2018-49 IE2018-67 |
In the millimeter wave CMOS circuit, the slow wave transmission line is used for a device that couples and decouples sig... [more] | CPM2018-88 ICD2018-49 IE2018-67 pp.3-7 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 15:20 |
Hiroshima | Satellite Campus Hiroshima | Millimeter wave band CMOS low noise amplifier design Kyoya Takegawa, Shuhei Amakawa, Takeshi Yoshida, Minoru Fujishima (Hiroshima Univ.) CPM2018-89 ICD2018-50 IE2018-68 |
[more] | CPM2018-89 ICD2018-50 IE2018-68 pp.9-12 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 15:45 |
Hiroshima | Satellite Campus Hiroshima | Design method of millimeter wave CMOS amplifier circuit with flat frequency characteristics Shota Kohara, Shuhei Amakawa, Takeshi Yoshida, Minoru Fujishima (Hiroshima Univ.) CPM2018-90 ICD2018-51 IE2018-69 |
High-speed wireless communication using a wideband in the millimeter wave is expected. In order to realize this, millime... [more] | CPM2018-90 ICD2018-51 IE2018-69 pp.13-16 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 15:55 |
Hiroshima | Satellite Campus Hiroshima | Malleable Task Scheduling for Energy Minimization on Heterogeneous Multicores Hiroki Nishikawa, Kana Shimada (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-63 DC2018-49 |
[more] | VLD2018-63 DC2018-49 pp.171-176 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 16:20 |
Hiroshima | Satellite Campus Hiroshima | Communication-Aware Scheduling for Data-Parallel Tasks Kana Shimada (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.) VLD2018-64 DC2018-50 |
[more] | VLD2018-64 DC2018-50 pp.177-182 |
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