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Technical Committee on Integrated Circuits and Devices (ICD) (Searched in: 2010)
Search Results: Keywords 'from:2010-04-22 to:2010-04-22'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2010-04-22 09:00 |
Kanagawa | Shonan Institute of Tech. | [Invited Talk]
A Configurable SRAM with Constant-Negative-Level Write Buffer for Low Voltage Operation with 0.149μm2 Cell in 32nm High-k Metal Gate CMOS Yuki Fujimura, Osamu Hirabayashi, Takahiko Sasaki, Azuma Suzuki, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Gou Fukano, Akira Katayama, Yusuke Niki, Tomoaki Yabe (Toshiba Corp.)  ICD2010-1 |
This paper presents a configurable SRAM for low voltage operation with Constant-Negative-Level Write Buffer (CNL-WB) and... [more] | ICD2010-1 pp.1-6 |
| ICD | 2010-04-22 09:50 |
Kanagawa | Shonan Institute of Tech. | [Invited Talk]
Challenging for an ultra low-voltage SRAM by innovative design circuits and device technologies
-- A 0.5V 100MHz PD-SOI SRAM using Asymmetric MOSFET and Forward Body Bias -- Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Yuuichi Hirano, Toshiaki Iwamatsu, Yuji Kihara (Renesas Electronics) ICD2010-2 |
We investigate 0.5V 6T-SRAM with asymmetric MOSFET, which contributes to enhance the read and write margin. We also intr... [more] | ICD2010-2 pp.7-12 |
| ICD | 2010-04-22 10:50 |
Kanagawa | Shonan Institute of Tech. | A 45nm 0.6V Cross-Point 8T SRAM with Negative Biased Read/Write Assist Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Yasunobu Nakase, Hirofumi Shinohara (Renesas Electronics) ICD2010-3 |
We propose a new design solution for embedded SRAM macros with cross point 8T-SRAM for low operating voltage and power. ... [more] | ICD2010-3 pp.13-16 |
| ICD | 2010-04-22 11:15 |
Kanagawa | Shonan Institute of Tech. | A 40-nm Low-power SRAM with Multi-stage Replica-Bitline Scheme for Reducing Timing Variation Shigenobu Komatsu, Masanao Yamaoka (HITACHI), Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki (Renesas Technology Corp.), Kenichi Osada (HITACHI) ICD2010-4 |
A multi-stage replica bitline scheme for reducing access time by suppressing enable timing variation of a sense amplifie... [more] | ICD2010-4 pp.17-21 |
| ICD | 2010-04-22 11:40 |
Kanagawa | Shonan Institute of Tech. | 32% Lower Active Power, 42% Lower Leakage Current Ferroelectric 6T-SRAM with VTH Self-Adjusting Function for 60% Larger Static Noise Margin (SNM) Shuhei Tanakamaru, Teruyoshi Hatanaka, Ryoji Yajima (Univ. of Tokyo), Mitsue Takahashi, Shigeki Sakai (AIST), Ken Takeuchi (Univ. of Tokyo) ICD2010-5 |
A 0.5V 6T-SRAM with ferroelectric (Fe-) FETs is proposed and experimentally demonstrated for the first time. The propose... [more] | ICD2010-5 pp.23-28 |
| ICD | 2010-04-22 12:05 |
Kanagawa | Shonan Institute of Tech. | Low-VT CMOS Preamplifier for 0.5-V Gigabit-DRAM Arrays Akira Kotabe, Yoshimitsu Yanagawa, Satoru Akiyama, Tomonori Sekiguchi (Hitachi) ICD2010-6 |
A novel low-VT CMOS preamplifier was developed for low-power and high-speed gigabit DRAM arrays. The sensing time of the... [more] | ICD2010-6 pp.29-33 |
| ICD | 2010-04-22 13:30 |
Kanagawa | Shonan Institute of Tech. | [Invited Talk]
A 64Mbit MRAM with Clamped-Reference and Adequate-Reference Schemes Kenji Tsuchida, Tsuneo Inaba, Katsuyuki Fujita, Yoshihiro Ueda, Takafumi Shimizu, Yoshiaki Asao, Takeshi Kajiyama, Masayoshi Iwayama, Sumio Ikegawa, Tatsuya Kishi, Tadashi Kai, Minoru Amano, Naoharu Shimomura, Hiroaki Yoda, Yohji Watanabe (TOSHIBA) ICD2010-7 |
A 64Mb spin-transfer-torque MRAM in 65nm CMOS is developed. 47mm2 die uses 0.3584um2 cell with the perpendicular-TMR dev... [more] | ICD2010-7 pp.35-40 |
| ICD | 2010-04-22 14:20 |
Kanagawa | Shonan Institute of Tech. | [Invited Talk]
Overview of Chain FeRAM Technology and Scalable Shield-Bitline-Overdrive Technique Daisaburo Takashima, Hidehiro Shiga, Daisuke Hashimoto, Tadashi Miyakawa, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima (Toshiba) ICD2010-8 |
This paper presents an overview of chain FeRAM technology, and a new scalable shield-bitline-overdrive technique. First,... [more] | ICD2010-8 pp.41-46 |
| ICD | 2010-04-22 15:20 |
Kanagawa | Shonan Institute of Tech. | Fabrication of a Nonvolatile Lookup-Table Circuit Chip Using Magneto/Semiconductor-Hybrid Structure for an Immediate-Power-Up Field Programmable Gate Array Daisuke Suzuki, Masanori Natsui, Shoji Ikeda (Tohoku Univ.), Haruhiro Hasegawa, Katsuya Miura, Jun Hayakawa (ARL, Hitachi, Ltd.), Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu (Tohoku Univ.) ICD2010-9 |
This paper presents a nonvolatile LUT (Lookup-Table) circuit in FPGA (Field-Programmable Gate Array) using a MTJ (Magnet... [more] | ICD2010-9 pp.47-52 |
| ICD | 2010-04-22 15:45 |
Kanagawa | Shonan Institute of Tech. | A 32-Mb SPRAM with localized bi-directional write driver, '1'/'0' dual-array equalized reference scheme, and 2T1R memory cell layout Riichiro Takemura, Takayuki Kawahara, Katsuya Miura, Hiroyuki Yamamoto, Jun Hayakawa, Nozomu Matsuzaki, Kazuo Ono, Michihiko Yamanouchi, Kenchi Ito, Hiromasa Takahashi (Hitachi), Shoji Ikeda (Tohoku Univ.), Haruhiro Hasegawa, Hideyuki Matsuoka (Hitachi), Hideo Ohno (Tohoku Univ.) ICD2010-10 |
A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ... [more] | ICD2010-10 pp.53-57 |
| ICD | 2010-04-23 09:30 |
Kanagawa | Shonan Institute of Tech. | Ferroelectric (Fe)-NAND Flash Memory with Non-volatile Page Buffer for Data Center Application Enterprise Solid-State Drives (SSD) Teruyoshi Hatanaka, Ryoji Yajima (Univ. of Tokyo), Takeshi Horiuchi, Shouyu Wang, Xizhen Zhang, Mitsue Takahashi, Shigeki Sakai (AIST), Ken Takeuchi (Univ. of Tokyo) ICD2010-11 |
A ferroelectric (Fe)-NAND flash memory with a non-volatile (NV) page buffer is proposed. The data fragmentation in a ran... [more] | ICD2010-11 pp.59-64 |
| ICD | 2010-04-23 09:55 |
Kanagawa | Shonan Institute of Tech. | Multi-stacked 1G cell/layer Pipe-shaped BiCS Flash Memory Takashi Maeda, Kiyotaro Itagaki, Tomoo Hishida, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kido, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Yoshihisa Iwata, Yohji Watanabe (Toshiba) ICD2010-12 |
(To be available after the conference date) [more] | ICD2010-12 pp.65-68 |
| ICD | 2010-04-23 10:20 |
Kanagawa | Shonan Institute of Tech. | Design Technology of stacked NAND FeRAM Koichi Sugano, Shigeyoshi Watanabe (Shonan Inst. of Tech.) ICD2010-13 |
[more] | ICD2010-13 pp.69-74 |
| ICD | 2010-04-23 10:45 |
Kanagawa | Shonan Institute of Tech. | Study of stacked NOR type MRAM Shouto Tamai, Shigeyoshi Watanabe (sit) ICD2010-14 |
[more] | ICD2010-14 pp.75-80 |
| ICD | 2010-04-23 11:25 |
Kanagawa | Shonan Institute of Tech. | [Invited Talk]
High-Speed Memory Interfaces
-- DDR/GDDR-DRAM -- Yasuhiro Takai (Elpida) ICD2010-15 |
(To be available after the conference date) [more] | ICD2010-15 pp.81-82 |
| ICD | 2010-04-23 13:45 |
Kanagawa | Shonan Institute of Tech. | [Invited Talk]
Non-contact Chip-to-Chip Interfaces for 3D System Integration Hiroki Ishikuro, Tadahiro Kuroda (Keio Univ.) ICD2010-16 |
Low cost, small size, low power, and wide-band non-contact area interfaces for inter-chip links in 3-D system integratio... [more] | ICD2010-16 pp.83-88 |
| ICD | 2010-04-23 14:35 |
Kanagawa | Shonan Institute of Tech. | A 2.5Gb/s/ch 4PAM Inductive-Coupling Transceiver for Non-Contact Memory Card Yasuhiro Take, Shusuke Kawai, Hiroki Ishikuro, Tadahiro Kuroda (Keio Univ.) ICD2010-17 |
A 2.5Gb/s/ch 4PAM inductive-coupling link is developed for non-contact memory cards. The data rate is 3× higher than tha... [more] | ICD2010-17 pp.89-92 |
| ICD | 2010-04-23 15:15 |
Kanagawa | Shonan Institute of Tech. | An 8Tb/s 1pJ/b 0.8mm2/Tb/s QDR Inductive-Coupling Interface Between 65nm CMOS GPU and 0.1um DRAM Noriyuki Miura, Kazutaka Kasuga, Mitsuko Saito, Tadahiro Kuroda (Keio Univ.) ICD2010-18 |
An 8Tb/s 1pJ/b 0.8mm2/Tb/s inductive-coupling interface between 65nm CMOS GPU and 0.1um DRAM is developed. BER<10-16 ope... [more] | ICD2010-18 pp.93-97 |
| ICD | 2010-04-23 15:40 |
Kanagawa | Shonan Institute of Tech. | A 2Gb/s 1.8pJ/b/chip Inductive-Coupling Through-Chip Bus for 128-Die NAND-Flash Memory Stacking Mitsuko Saito, Noriyuki Miura, Tadahiro Kuroda (Keio Univ.) ICD2010-19 |
128 chips are stacked using a spiral stair stacking scheme. The controller accesses a random memory chip at 2Gb/s by ind... [more] | ICD2010-19 pp.99-102 |
| ICD | 2010-04-23 16:05 |
Kanagawa | Shonan Institute of Tech. | [依頼講演]Digital Rosetta Stone: A Sealed Permanent Memory with Inductive-Coupling Power and Data Link Yuxiang Yuan, Noriyuki Miura (Keio Univ.), Shigeki Imai (Sharp), Hiroyuki Ochi (Kyoto Univ.), Tadahiro Kuroda (Keio Univ.) ICD2010-20 |
A permanent memory system is prototyped in 0.18µm CMOS. Data is stored in MROM, and stacked wafers are completely s... [more] | ICD2010-20 pp.103-105 |
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