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Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD, HWS [detail] 2020-10-26
09:25		 Online Online Power Analysis Attack Using Pipeline Scheduling on Pairing Hardware
Mitsufumi Yamazaki, Junichi Sakamoto, Tsutomu Matsumoto (YNU) HWS2020-26 ICD2020-15		 To reduce the latency of pairing calculation for advanced cryptography, hardware implementations with pipelined modular ... [more] HWS2020-26 ICD2020-15
pp.7-12
HWS, ICD 2018-10-29
14:30		 Osaka Kobe Univ. Umeda Intelligent Laboratory An Acceleration of Compressed Squaring for Pairing Implementation with Pipeline Modular Multiplier
Yota Okuaki, Junichi Sakamoto, Naoki Yoshida, Daisuke Fujimoto, Tsutomu Matsumoto (YNU) HWS2018-50 ICD2018-42		 One of the biggest problems of the emerging cyber-physical and cloud computing systems is how to ensure security with en... [more] HWS2018-50 ICD2018-42
pp.19-24
VLD 2009-03-11
14:25		 Okinawa   Area Optimized Pipeline Scheduling with Initiation Interval and Allocation Constraints
Sho Kodama, Yusuke Matsunaga (Kyushu Univ.) VLD2008-131		 In this paper, a pipeline scheduling algorithm for minimizing total circuit area under throughput constraint
is present... [more]		 VLD2008-131
pp.29-34
VLD, ICD 2008-03-07
09:40		 Okinawa TiRuRu Enhancing Multimedia Processing by Wave-Pipelining a Multifunctional Execution Unit
Kazunori Noda, Atuko Yokoyama, Hiroki Takeda, Masa-aki Fukase, Tomoaki Sato (Hirosaki Univ.) VLD2007-157 ICD2007-180		 A multimedia mobile processor HCgorilla developed for ubiquitous network was built in Java CPU, cipher logic, and floati... [more] VLD2007-157 ICD2007-180
pp.7-12
VLD, ICD, DC, IPSJ-SLDM 2005-12-02
11:25		 Fukuoka Kitakyushu International Conference Center A Method for Allocating Bus Transfer and Task Execution Cycles Based on Scenarios
Seiji Yamaguchi, Tadaaki Tanimoto, Akio Nakata, Teruo Higashino (Osaka Univ.) 		In designing a bus system, it is important to derive a real-time constraint (the number of available cycles) for each ta... [more] VLD2005-80 ICD2005-175 DC2005-57
pp.25-30
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