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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-24 14:20 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Three-Dimensional Accelerator Architecture for Image Recognition Shinya Ueno, Gauthier Lovic Eric, Koji Inoue, Kazuaki Murakami (Kyushu Univ.)  SIP2011-63 ICD2011-66 IE2011-62 |
Image recognition used widely in several areas needs high-performance and low power processor. Accelerator is an effecti... [more] | SIP2011-63 ICD2011-66 IE2011-62 pp.7-12 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-24 14:45 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Architecture of a Dynamically Reconfigurable VLSI Processor Based on Register-Transfer-Level Packet Transfer Yoshichika Fujioka (Hachinohe Inst. of Tech.), Sho Takizawa, Michitaka Kameyama (Tohoku Univ.) SIP2011-64 ICD2011-67 IE2011-63 |
Register-transfer-level packet routing scheme is proposed for intra-chip data transfer to make the size of configuration... [more] | SIP2011-64 ICD2011-67 IE2011-63 pp.13-18 |
| RECONF | 2011-09-27 11:00 |
Aichi | Nagoya Univ. | Performance Evaluation of Power Monitoring Programs on Reconfigurable Processor DS-HIE Kyohei Tao, Takatoshi Tamaoki, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.) RECONF2011-36 |
In recently years, a smart grid has been emerging as a new power network. As the smart grid needs a smart meter, a sma... [more] |
RECONF2011-36 pp.81-86 |
| RECONF | 2011-09-27 13:20 |
Aichi | Nagoya Univ. | Design and Implementation of Adaptive Viterbi Decoder using Dynamic Reconfigurable System STP Engine Yuken Kishimoto, Takao Toi, Takaaki Miyajima, Hideharu Amano (Keio Univ.) RECONF2011-38 |
Implementing Viterbi Algorithm that is the decoding method of Convolutional code on hard-wired logic, in order to variou... [more] | RECONF2011-38 pp.93-98 |
| CS, SIP, CAS | 2011-03-03 10:50 |
Okinawa | Ohhamanobumoto memorial hall (Ishigaki)( | A Modular Low Cost Hardware TCP/IP Stack Implementation Adding Direct Network Capabilities to Same On-Chip Embedded Applications Using Xilinx Spartan3 FPGA Nadav Bergstein, Hakaru Tamukoh, Masatoshi Sekine (Tokyo Univ. of Agric and Tech.) CAS2010-128 SIP2010-144 CS2010-98 |
As multi-processor based computers and electronic devices become the norm, a further emphasis is made on achieving task... [more] |
CAS2010-128 SIP2010-144 CS2010-98 pp.155-160 |
| VLD | 2011-03-03 14:10 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | A Circuit Synthesis for Dynamic Reconfigurable Processor Nobuyuki Araki, Takashi Kambe (Kinki Univ.) VLD2010-131 |
Dynamic reconfiguraible processors can implement large-scale and complicated circuits by changing its configurations dur... [more] | VLD2010-131 pp.87-92 |
| ICD, IPSJ-ARC | 2011-01-21 11:40 |
Kanagawa | Keio University (Hiyoshi Campus) | Acceleration of Block Matching by using Multiple Alignments on Heterogeneous Multi-Core Processor Yoshitaka Hiramatsu (Hitachi), Hasitha Muthumala Waidyasooriya, Masanori Hariyama (Tohoku Univ.), Tohru Nojiri, Kunio Uchiyama (Hitachi) |
The large data-transfer time among different cores and data-supply time to arithmetic unit is a big problem in heterogen... [more] | ICD2010-136 pp.57-62 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-17 14:10 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Power reduction in Dynamically Reconfigurable Processor by Dynamically VDD Switching and a mapping technique to reduce energy overhead Tatsuya Yamamoto (Shibaura Institute), Kazuei Hironaka (Keio Univ.), Yuki Hayakawa (Shibaura Institute), Masayuki Kimura, Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Institute) VLD2010-92 CPSY2010-47 RECONF2010-61 |
This paper describes a dynamic VDD switching technique to reduce energy dissipation of Dynamically Reconfigurable Proces... [more] | VLD2010-92 CPSY2010-47 RECONF2010-61 pp.49-54 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 14:30 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Implementation of Dynamic Reconfigurable Processor with Multi-Accelerator Shuhei Igari, Junji Kitamichi, Yuichi Okuyama, Kenichi Kuroda (Aizu Univ.) VLD2010-108 CPSY2010-63 RECONF2010-77 |
Recently, System on a Chip (SoC) has problems increasing of the scale of circuit and design cost, because SoC contains m... [more] | VLD2010-108 CPSY2010-63 RECONF2010-77 pp.163-168 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 14:50 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Silent Large Datapath : A Ultra Low Power Accelarater Yoshihiro Yasuda, Nobuaki Ozaki, Masayuki Kimura, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano (Keio Univ.), Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. Tech.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Masaaki Kondo (Univ. of Electro-Communications) VLD2010-109 CPSY2010-64 RECONF2010-78 |
Silent Large Datapath (SLD) is a low power reconfigurable accelerator for high performance embedded systems. By using a... [more] |
VLD2010-109 CPSY2010-64 RECONF2010-78 pp.169-174 |
| ICD | 2010-12-16 15:10 |
Tokyo | RCAST, Univ. of Tokyo | [Poster Presentation]
Design of An FU Network for Array Accelerators Suguru Ooue, Takuya Iwakami, Kazuhiro Yoshimura, Takashi Nakada, Yasuhiko Nakashima (NAIST) ICD2010-115 |
We have proposed Linear Array Pipeline Processor (LAPP) as a special implementation of Function Unit (FU) array based ac... [more] | ICD2010-115 pp.97-99 |
| ICD | 2010-12-17 14:15 |
Tokyo | RCAST, Univ. of Tokyo | Fine Grained Time Sharing to Extend Capacity of FU Array Takuya Iwakami, Kazuhiro Yoshimura, Kodai Mori, Takashi Nakada, Yasuhiko Nakashima (NAIST) ICD2010-123 |
We have proposed Linear Array Pipeline Processor (LAPP) which can map popular VLIW codes onto FU array and execute them... [more] |
ICD2010-123 pp.141-146 |
| VLD | 2010-09-27 14:25 |
Kyoto | Kyoto Institute of Technology | Accelerator-Centric Task Allocation Based on Algorithm Transformation for Heterogeneous Multicore Processors Masanori Hariyama, Hasitha Muthumala Waidyasooriya, Michitaka Kameyama (Tohoku Univ.) VLD2010-43 |
Heterogeneous multi-core processors are attracted by the media processing applications due to their capability of drawi... [more] |
VLD2010-43 pp.7-12 |
| RECONF | 2010-09-16 13:50 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | A Consideration of Reconfigurable Processor for RSA Cryptography Takatoshi Tamaoki, Kazuya Tanigawa, Tetsuo Hironaka (hcu) RECONF2010-22 |
Encrypting and decrypting RSA require many exponentiation calculations, and modulo calculation with bit-with wider than... [more] |
RECONF2010-22 pp.25-30 |
| RECONF | 2010-09-16 15:25 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | Evaluation of Multiple-Precision Floating-Point Accelerator HP-DSFP through Applications. Yuki Yoshioka, Tomoyuki Kawamoto, Taiga Ban, Kazuya Tanigawa, Tetsuo Hironaka (HCU) RECONF2010-25 |
In recent years, many kinds of scientific application programs, such as Fluid analysis, Feynman loop integrals and conju... [more] | RECONF2010-25 pp.43-48 |
| RECONF | 2010-09-17 11:00 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | Removing context memory from Multi-context Dynamically Reconfigurable Processors Hideharu Amano, Masayuki Kimura, Nobuaki Ozaki (Keio Univ.) RECONF2010-34 |
Although context memory or configuration cache is a key mechanism for quick dyna mic reconfiguration of multi-context ... [more] |
RECONF2010-34 pp.97-102 |
| RECONF | 2010-05-13 14:55 |
Nagasaki | A study on multicore designed MuCCRA3 : dynamically reconfigurable processor array Eiichi Sasaki, Yoshiki Saito, Masayuki Kimura, Hideharu Amano (Keio Univ.) RECONF2010-4 |
Recently, since a mobile device is required to provide various functions, a lot of specialized hardware modules must be... [more] |
RECONF2010-4 pp.19-24 |
|
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-UBI, IPSJ-MBL [detail] | 2010-03-28 11:15 |
Tokyo | Design and Evaluation of An Instruction Scheduler for FU Array Processor Kazuhiro Yoshimura, Munehisa Agari, Takashi Nakada, Yasuhiko Nakashima (NAIST) CPSY2009-94 DC2009-91 |
Recently, we have proposed Linear Array Pipeline Processor (LAPP) that improves energy efficiency for various workloads ... [more] | CPSY2009-94 DC2009-91 pp.511-516 |
|
| RCS, AN, MoNA, SR (Joint) |
2010-03-04 11:10 |
Kanagawa | YRP | Software Based Modem with Dynamic Reconfigurable Processor Ren Sakata, Daisuke Takeda, Noritaka Deguchi, Tatsuma Hirano, Takashi Yoshikawa (Toshiba Corp.) SR2009-105 |
Software Defined Radio (SDR) techniques are expected to increase convenience of wireless equipments by providing plural ... [more] | SR2009-105 pp.99-104 |
| ICD, IPSJ-ARC, IPSJ-EMB | 2010-01-29 13:25 |
Tokyo | T.B.D. | Developing an Architecture for a Single-Flux Quantum Based Reconfigurable Accelerator Farhad Mehdipour (Kyushu Univ.), Hiroaki Honda (ISIT), Hiroshi Kataoka, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) ICD2009-111 |
As a solution to gain high performance computation, a large scale reconfigurable data-path (LSRDP) processor is introdu... [more] |
ICD2009-111 pp.99-104 |
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