Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
CS, CAS, SIP |
2014-03-06 13:50 |
Osaka |
Osaka City University Media Center |
A study on visualization of auscultation-based blood pressure measurement Nobuhito Ochi, Yusuke Ohtsuka, Yusuke Katsuki, Mingyu Li, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Hiromi Kodama, Kiyako Takai, Nagisa Okada (Univ. of Occupetional and Environmental Health) CAS2013-107 SIP2013-153 CS2013-120 |
Blood pressure measurement by Korotkoff sounds auscultation is an essential skill for health care workers, but the skill... [more] |
CAS2013-107 SIP2013-153 CS2013-120 pp.97-102 |
IE, ICD, VLD, IPSJ-SLDM [detail] |
2013-10-08 11:25 |
Aomori |
|
A Delay-Locked Loop with Multi-Level Channel Length Decomposed Programming Delay Elements Yu Zhang, Mingyu Li, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Bo Yang (Design Algorithm Lab) VLD2013-59 ICD2013-83 IE2013-59 |
Variable delay elements are often used in various types
of high-speed integrated circuits,
mainly intended for delay c... [more] |
VLD2013-59 ICD2013-83 IE2013-59 pp.71-76 |
IE, ICD, VLD, IPSJ-SLDM [detail] |
2013-10-08 11:50 |
Aomori |
|
A 9-bit, 20MS/s SAR ADC with A Design Strategy by Synthesizing Consideration of Layout-Dependent Effects Gong Chen, Mingyu Li, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Bo Yang (Design Algorithm Lab) VLD2013-60 ICD2013-84 IE2013-60 |
In nano-scale manufacturing processes of integrated circuits,
a impact of layout-dependent effects (LDEs)
to circuit p... [more] |
VLD2013-60 ICD2013-84 IE2013-60 pp.77-82 |
VLD, IPSJ-SLDM |
2013-05-16 09:00 |
Fukuoka |
Kitakyushu International Conference Center |
Performance-driven SRAM Macro Design with Parameterized Cell Considering Layout-dependent Effects Yu Zhang, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2013-1 |
In nano-scale process, shallow trench isolation (STI) stress and well
proximity effect (WPE) affect the threshold volta... [more] |
VLD2013-1 pp.1-6 |
VLD |
2013-03-06 13:40 |
Okinawa |
Okinawa Seinen Kaikan |
A Delay Control Circuit with Channel Length Decomposition and Its Application Yuichi Toyota, Yuki Nakashima, Toru Fujimura, Shigetoshi Nakatake (Univ of Kitakyushu) VLD2012-158 |
In recent years, as the progress of the semiconductor manufacturing, the variations of circuit performance due to device... [more] |
VLD2012-158 pp.123-128 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 09:25 |
Fukuoka |
Centennial Hall Kyushu University School of Medicine |
Routability-oriented Common-Centroid Capacitor Array Generation Jing Li, Bo Yang (Design Algorithm Lab.), Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2012-89 DC2012-55 |
We address layout generation of on-chip matched capacitors with the high relative accuracy. Unit capacitors are placed i... [more] |
VLD2012-89 DC2012-55 pp.171-175 |
IE, SIP, ICD, VLD, IPSJ-SLDM [detail] |
2012-10-19 10:15 |
Iwate |
Hotel Ruiz |
A 9-bit 10MSps SAR ADC with Double Input Range for Supply Voltage Gong Chen, Yu Zhang, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Bo Yang, Jing Li (Design Algorithm Lab.) VLD2012-49 SIP2012-71 ICD2012-66 IE2012-73 |
This paper presents a pre-charge VCM-based method for 1.2V 9-bit 10MSps Successive Approximation
Register (SAR) ADC. Th... [more] |
VLD2012-49 SIP2012-71 ICD2012-66 IE2012-73 pp.49-53 |
IE, SIP, ICD, VLD, IPSJ-SLDM [detail] |
2012-10-19 14:30 |
Iwate |
Hotel Ruiz |
CMOS Op-amp Circuit Synthesis with Geometric Programming Yu Zhang, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Bo Yang, Jing Li (Design Algorithm Lab.) VLD2012-54 SIP2012-76 ICD2012-71 IE2012-78 |
This work presents a 6T SRAM design in nanometer process via geometric programming (GP). We adopt the transistor array (... [more] |
VLD2012-54 SIP2012-76 ICD2012-71 IE2012-78 pp.77-82 |
IPSJ-SLDM, VLD |
2012-05-31 10:20 |
Fukuoka |
Kitakyushu International Conference Center |
A Comparator Energy Model Considering Shallow Trench Isolation by Geometric Programming Gong Chen, Yu Zhang, Bo Yang, Qing Dong, Shigetoshi Nakatake (Kitakyushu Univ.) VLD2012-8 |
In low power analog circuit designs, the current variation caused by the STI stress must be taken into
account. In this... [more] |
VLD2012-8 pp.43-48 |
VLD |
2011-09-26 14:00 |
Fukushima |
University of Aizu |
A transistor-level symmetrical layout generation method for analog device Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2011-40 |
[more] |
VLD2011-40 pp.1-4 |
VLD |
2011-09-26 14:25 |
Fukushima |
University of Aizu |
CMOS Op-amp Circuit Synthesis with Geometric Programming Models for Layout-Dependent Effects Yu Zhang, Gong Chen, Qing Dong, Jing Li, Bo Yang, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2011-41 |
[more] |
VLD2011-41 pp.5-10 |
VLD |
2011-03-02 16:20 |
Okinawa |
Okinawaken-Danjo-Kyodo-Sankaku Center |
Reusable Constraints of Nano-watt BGR Circuits in CMOS Process Migration Gong Chen, Delong Yin, Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2010-123 |
[more] |
VLD2010-123 pp.43-47 |
VLD |
2011-03-04 11:15 |
Okinawa |
Okinawaken-Danjo-Kyodo-Sankaku Center |
On Realization and Evaluation of Capacitors in Analog Integrated Circuits Atsushi Ochi, Ryoei Shimazu, Toru Fujimura, Shigetoshi Nakatake (Univ.of Kitakyushu) VLD2010-140 |
As proceeding to a deep submicron era,
the area efficiency of and the precision of passive components have become
impo... [more] |
VLD2010-140 pp.141-146 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-12-01 13:55 |
Fukuoka |
Kyushu University |
Analysis of Channel Decomposition for Structured Analog Layout and Low-power Applications Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2010-79 DC2010-46 |
[more] |
VLD2010-79 DC2010-46 pp.161-166 |
VLD |
2010-09-28 10:25 |
Kyoto |
Kyoto Institute of Technology |
Analog Layout Retargeting with Constraint Extraction by Matching of Fundamental Circuit Components and Layout Regularity Kazuhiko Shibata, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2010-49 |
[more] |
VLD2010-49 pp.43-48 |
VLD |
2010-09-28 10:50 |
Kyoto |
Kyoto Institute of Technology |
Regularity-Oriented Compaction with Z-cut Perturbation Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2010-50 |
[more] |
VLD2010-50 pp.49-54 |
CAS, MSS, VLD, SIP |
2010-06-21 11:40 |
Hokkaido |
Kitami Institute of Technology |
Layout-Aware Variation Modeling and Its Application to Opamp Design Kouta Shinohara, Mihoko Hidaka, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu) CAS2010-7 VLD2010-17 SIP2010-28 CST2010-7 |
As geometrical scaling of the transistor dimensions, such as feature
size and supply voltage, has dominated the semicon... [more] |
CAS2010-7 VLD2010-17 SIP2010-28 CST2010-7 pp.37-41 |
VLD, IPSJ-SLDM |
2010-05-20 14:20 |
Fukuoka |
Kitakyushu International Conference Center |
Variation Modeling of Current Sources by D/A Converter Analysis Bo Liu, Qing Dong, Bo Yang, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2010-10 |
[more] |
VLD2010-10 pp.85-89 |
VLD |
2010-03-10 13:55 |
Okinawa |
|
Analog Macro Layout Generation Based on Regular Bulk Structure Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2009-100 |
[more] |
VLD2009-100 pp.7-12 |
VLD |
2010-03-10 15:50 |
Okinawa |
|
Variation-Tolerant Decomposition of MOS Transistor Bo Liu, Atsushi Ochi, Shigetoshi Nakatake (Univ. of Kitakyushu) VLD2009-104 |
Aiming at the layout automation based on the regular bulk structure
in MOS analog circuits, we study how to decompose a... [more] |
VLD2009-104 pp.31-36 |