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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 9 of 9  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
PRMU, SP, WIT, ASJ-H 2016-06-13
14:00
Tokyo   Improvement and evaluation of emotional speech conversion method using difference between emotional and neutral acoustic features of another speaker
Reiko Takou, Kazuo Onoe, Nobumasa Seiyama, Atsushi Imai (NHK), Tohru Takagi (NHK-ES) PRMU2016-41 SP2016-7 WIT2016-7
 [more] PRMU2016-41 SP2016-7 WIT2016-7
pp.35-39
SDM, ICD 2011-08-26
13:40
Toyama Toyama kenminkaikan Ultra low noise in-substrate-bitline sense amplifier for 4F2 DRAM array
Yoshimitsu Yanagawa, Tomonori Sekiguchi, Akira Kotabe, Kazuo Ono, Riichiro Takemura (Hitachi) SDM2011-89 ICD2011-57
An in-substrate-bitline sense amplifier (SA) with an array-noise-gating (ANG) scheme for stable sensing operation in a 4... [more] SDM2011-89 ICD2011-57
pp.93-97
ICD 2011-04-18
10:00
Hyogo Kobe University Takigawa Memorial Hall [Invited Talk] Trends and Multi-level-cell Technology of Spin Transfer Torque Memory
Takashi Ishigaki, Takayuki Kawahara, Riichiro Takemura, Kazuo Ono, Kenchi Ito (Hitachi), Hideo Ohno (Tohoku U.) ICD2011-1
A MLC (Multi-level cell) SPRAM (Spin transfer torque RAM) with series-stacked MTJs (Magnetic tunnel junctions) was devel... [more] ICD2011-1
pp.1-5
ICD 2011-04-19
14:00
Hyogo Kobe University Takigawa Memorial Hall 1-Tbyte/s 1-Gbit Multicore DRAM Architecture using 3-D Integration for High-throughput Computing
Kazuo Ono, Yoshimitsu Yanagawa, Akira Kotabe, Tomonori Sekiguchi (Hitachi, CRL) ICD2011-15
A novel multicore DRAM architecture with an ultra high bandwidth and a large capacity is proposed for high throughput co... [more] ICD2011-15
pp.81-86
SDM 2010-11-11
13:00
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Trends of Magnetic Memory; Multi-Level-Cell Spin Transfer Torque Memory
Takashi Ishigaki, Takayuki Kawahara, Riichiro Takemura, Kazuo Ono, Kenchi Ito (Hitachi), Hideo Ohno (Tohoku U.) SDM2010-173
A MLC (Multi-level cell) SPRAM (Spin transfer torque RAM) with series-stacked MTJs (Magneto tunnel junctions) was develo... [more] SDM2010-173
pp.11-15
ICD, SDM 2010-08-26
13:00
Hokkaido Sapporo Center for Gender Equality 1-Tbyte/s 1-Gbit 3-D DRAM Architecture for High Throughput Computing
Yoshimitsu Yanagawa, Kazuo Ono, Akira Kotabe, Tomonori Sekiguchi (Hitachi) SDM2010-131 ICD2010-46
A novel DRAM architecture with an ultra high bandwidth is proposed for high throughput computing. The proposed architect... [more] SDM2010-131 ICD2010-46
pp.39-44
ICD 2010-04-22
15:45
Kanagawa Shonan Institute of Tech. A 32-Mb SPRAM with localized bi-directional write driver, '1'/'0' dual-array equalized reference scheme, and 2T1R memory cell layout
Riichiro Takemura, Takayuki Kawahara, Katsuya Miura, Hiroyuki Yamamoto, Jun Hayakawa, Nozomu Matsuzaki, Kazuo Ono, Michihiko Yamanouchi, Kenchi Ito, Hiromasa Takahashi (Hitachi), Shoji Ikeda (Tohoku Univ.), Haruhiro Hasegawa, Hideyuki Matsuoka (Hitachi), Hideo Ohno (Tohoku Univ.) ICD2010-10
A 32-Mb SPin-transfer torque RAM (SPRAM) chip was demonstrated with an access time of 32 ns and a cell write-time of 40 ... [more] ICD2010-10
pp.53-57
ITE-MMS, MRIS 2009-10-08
13:55
Fukuoka FUKUOKA traffic center [Invited Talk] Nonvolatile RAM using spin transfer torque magnetization reversal (SPRAM)
Hiromasa Takahashi, Kenchi Ito, Jun Hayakawa, Katsuya Miura, Hiroyuki Yamamoto, Michihiko Yamanouchi (ARL, Hitachi, Ltd.), Kazuo Ono, Riichiro Takemura, Takayuki Kawahara (CRL, Hitachi, Ltd.), Ryutaro Sasaki (RIEC Tohoku Univ.), Haruhiro Hasegawa (RIEC Tohoku Univ., ARL, Hitachi, Ltd.), Shoji Ikeda (RIEC Tohoku Univ.), Hideyuki Matsuoka (ARL, Hitachi, Ltd.), Hideo Ohno (RIEC Tohoku Univ.)
The SPRAM (Spin Transfer Torque MRAM) is one of nonvolatile memories that “writing” is done by that a magnetization in M... [more]
MW 2006-12-22
10:45
Ehime   Modal Matching Analysis of Radio Wave Propagation Over planar Mixed-Path
Hideaki Ikeda (Ehime Univ.), Yoshihiro Norimatsu (RNB), Kazuo Ono (Ehime Univ.)
 [more] MW2006-144
pp.1-6
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