|
|
All Technical Committee Conferences (Searched in: All Years)
|
|
Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
|
Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
VLD |
2016-03-01 09:00 |
Okinawa |
Okinawa Seinen Kaikan |
A Packet Lookup Engine LSI Based on Mismatch Detection and Hash Search Yoshifumi Kawamura, Kousuke Imamura (Kanazawa Univ.), Naoki Miura, Masami Urano, Satoshi Shigematsu (NTT), Tetsuya Matsumura (Nihon Univ.), Yoshio Matsuda (Kanazawa Univ.) VLD2015-118 |
Developing an extremely efficient packet inspection algorithm for lookup engines is important to realize a high throughp... [more] |
VLD2015-118 pp.43-48 |
CS |
2014-07-03 15:30 |
Kagoshima |
Minamitanecho Shoukoukai Kaigishitsu |
[Invited Talk]
Power Reduction and Demand Relaxation for Receiver by Optimizing Optical Power using BER for 10G-EPON Systems Namiko Ikeda, Hiroyuki Uzawa, Kazuhiko Terada, Satoshi Shigematsu, Hiroshi Koizumi, Masami Urano (NTT) CS2014-27 |
In 10G-EPON systems, an optical power of an ONU transmitter and a dynamic range for a burst receiver of an OLT is define... [more] |
CS2014-27 pp.61-65 |
CS, OCS (Joint) |
2014-01-23 09:30 |
Tokyo |
Hajijo-jima Ohgagou Kouminkan |
Power Reduction by Adaptively Optimizing Optical Power using Actual BER for 10G-EPON Systems Namiko Ikeda, Hiroyuki Uzawa, Kazuhiko Terada, Satoshi Shigematsu, Hiroshi Koizumi, Masami Urano (NTT) CS2013-96 |
10G-EPON systems are next generations of access network systems, and power consumptions of these systems increase becaus... [more] |
CS2013-96 pp.71-74 |
MWP, OPE, MW, EMT, EST, IEE-EMT [detail] |
2012-07-26 13:40 |
Hokkaido |
Hokkaido Univ. |
BER Calculation Modeling for 10G-EPON Systems Namiko Ikeda, Kazuhiko Terada, Hiroyuki Uzawa, Akihiko Miyazaki, Satoshi Shigematsu, Masami Urano, Tsugumichi Shibata (NTT) MW2012-31 OPE2012-24 EST2012-13 MWP2012-12 |
In 10G-EPON systems, the high speed access networks in the next generation, the upper limits of the bit error rate (BER)... [more] |
MW2012-31 OPE2012-24 EST2012-13 MWP2012-12 pp.47-52 |
VLD |
2012-03-06 13:10 |
Oita |
B-con Plaza |
10G/1G dual-rate EPON OLT LSI with dual encryption modes selected using DBA-information-based algorithm control Sadayuki Yasuda, Takahiro Hatano, Hiroki Suto, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata (NTT) VLD2011-124 |
For next-generation optical access systems, we developed a 10G/1G dual-rate EPON OLT LSI that fully conforms to the IEEE... [more] |
VLD2011-124 pp.25-30 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 10:55 |
Miyazaki |
NewWelCity Miyazaki |
A 22-Gb/s and over-33-mega-frame/s throughput bridge-function unit in a low-latency OLT LSI for the coexistence of 10G-EPON and GE-PON Shoko Ohteru, Tomoaki Kawamura, Hiroki Suto, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata (NTT) CPM2011-166 ICD2011-98 |
A multifunctional bridge function unit and buffer function unit were developed for the OLT LSI for the coexistence of 10... [more] |
CPM2011-166 ICD2011-98 pp.91-96 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 11:20 |
Miyazaki |
NewWelCity Miyazaki |
10G-EPON OLT and ONU LSIs for next-generation FTTx system Tomoaki Kawamura, Shoko Ohteru, Sadayuki Yasuda, Akihiko Miyazaki, Kenji Kawai, Ritsu Kusaba, Mamoru Nakanishi, Masami Urano, Tsugumichi Shibata (NTT) CPM2011-167 ICD2011-99 |
10G-EPON OLT and ONU LSIs that integrate the full functions confirming to the IEEE 802.3av standard were developed for n... [more] |
CPM2011-167 ICD2011-99 pp.97-102 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-30 10:45 |
Fukuoka |
Kyushu University |
FPGA design and test methodology for communication frame processinng Ritsu Kusaba, Kenji Kawai, Sadayuki Yasuda, Satoshi Shigematsu, Mamoru Nakanishi, Masami Urano (NTT) VLD2010-67 DC2010-34 |
For large-scale and high-speed frame processing on a FPGA board, we propose a new design method based on the property of... [more] |
VLD2010-67 DC2010-34 pp.73-78 |
VLD |
2009-03-12 11:05 |
Okinawa |
|
High-Speed Packet-Filter Circuit with Mismatch-Detection Circuit Naoki Miura, Satoshi Shigematsu, Takahiro Hatano (NTT), Yusuke Akamine (Kyushu Univ.), Mamoru Nakanishi, Masami Urano (NTT) VLD2008-143 |
(To be available after the conference date) [more] |
VLD2008-143 pp.101-106 |
|
|
|
Copyright and reproduction :
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
|
[Return to Top Page]
[Return to IEICE Web Page]
|