| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS, VLD [detail] | 2020-03-05 14:30 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
[Memorial Lecture]
Small-Area and Low-Power FPGA-Based Multipliers using Approximate Elementary Modules Yi Guo, Heming Sun, Shinji Kimura (Waseda Univ.)  VLD2019-117 HWS2019-90 |
[more] | VLD2019-117 HWS2019-90 p.137 |
| HWS, VLD [detail] | 2020-03-05 16:00 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
Approximate Floating Point Multiplier based on Shifting Addition Using Carry Signal from Second-Highest-Bit Jie Li, Yi Guo, Shinji Kimura (Waseda Univ.) VLD2019-120 HWS2019-93 |
Approximate computing (AC) sacrifices accuracy for better hardware performance since it relaxes the requirement of exact... [more] | VLD2019-120 HWS2019-93 pp.151-156 |
| EID, ITE-IDY, ITE-HI, ITE-3DMT, IEE-OQD, SID-JC [detail] | 2019-10-24 14:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Dispersion compensation for full-color virtual-imaging systems with a holographic off-axis mirror Fumiaki Watanabe (Tokyo Tech), Tomoya Nakamura (Tokyo Tech/JST), Shiho Trashima, Shunsuke Igarashi (Tokyo Tech), Shinji Kimura (Tokyo Tech/NTT DOCOMO), Yuji Aburakawa (NTT DOCOMO), Masahiro Yamaguchi (Tokyo Tech) |
[more] | |
| MBE | 2019-05-19 15:25 |
Niigata | Niigata University | Identification of Anaerobic Threshold with strucchange Takenori Aida, Hirofumi Nonaka, Kouji Hayami, Hisashi Uchiyama, Masahito Nagamori, Akira Shionoya (Nagaoka Univ. of Tech), Rika Kimoto (Fuji Women's Univ.), Mai Kobayashi (Seiryou Junior College. of Reha), Tsugumi Takayama, Shinji Kimura, Tohru Minamino (Niigata Univ. Med Dent Hosp) MBE2019-12 |
Recently, various exercise has been performed including the participation in citizens' marathon meet in various scenes b... [more] | MBE2019-12 pp.61-65 |
| EID, ITE-IDY, ITE-HI, ITE-3DMT, IEE-OQD, SID-JC [detail] | 2018-10-25 15:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg | Research of video communication system using holographic optical elements Shinji Kimura (DOCOMO), Tomoya Nakamura, Shunsuke Takahashi, Shunsuke Igarashi, Shiho Torashima, Masahiro Yamaguchi (Tokyo Tech), Yuji Aburakawa (DOCOMO) EID2018-3 |
To enhance “presence” on video-mediated communication system, we here noticed eye contacts in communication and confirme... [more] | EID2018-3 pp.21-24 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 11:20 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | Implementation and Optimization of Parallel Prefix Adder Using Majority Function Daiki Matsumoto, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2017-46 DC2017-52 |
In recent FPGAs and post CMOS devices, three-input majority operation can be efficiently realized and circuit configuration... [more] | VLD2017-46 DC2017-52 pp.109-114 |
| VLD | 2017-03-01 15:30 |
Okinawa | Okinawa Seinen Kaikan | High accuracy 8*8 approximate multiplier based on OR operation Yi Guo, Heming Sun, Canran Jin, Shinji Kimura (Waseda Univ.) VLD2016-105 |
Approximate computing is a promising approach for error-tolerate applications. Multipliers contribute more area and dela... [more] | VLD2016-105 pp.19-24 |
| VLD, IPSJ-SLDM | 2016-05-11 15:20 |
Fukuoka | Kitakyushu International Conference Center | MERP-CNN: A Memory-Efficient Reconfigurable Processor for Convolutional Neural Networks Based on FPGA Xushen Han, Dajiang Zhou, Shinji Kimura (Waseda Univ.) VLD2016-5 |
Convolutional neural network has been paid so much attention in many intelligent applications especially image pattern r... [more] | VLD2016-5 pp.47-52 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-20 09:50 |
Kanagawa | Hiyoshi Campus, Keio University | Control Signal Extraction for Backward Sequential Clock Gating Tomoya Goto, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2015-89 CPSY2015-121 RECONF2015-71 |
[more] | VLD2015-89 CPSY2015-121 RECONF2015-71 pp.97-102 |
| VLD, CPSY, RECONF, IPSJ-SLDM, IPSJ-ARC [detail] | 2016-01-21 14:15 |
Kanagawa | Hiyoshi Campus, Keio University | Write-Reduction using Encoding data on MLC for Non-Volatile Memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-107 CPSY2015-139 RECONF2015-89 |
There is a movement to use the non-volatile memory to the important main memory in von Neumann computer. Non-volatile m... [more] |
VLD2015-107 CPSY2015-139 RECONF2015-89 pp.221-225 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 15:00 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | A Circuit Area-Aware Bit-Write Reduction Code Generation for Non-Volatile Memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-76 DC2015-72 |
Recently, due to low leakage power and non-volatility, the non-volatile memory technology has advanced remarkably. Howe... [more] |
VLD2015-76 DC2015-72 pp.249-253 |
| VLD, IPSJ-SLDM | 2015-05-14 11:35 |
Fukuoka | Kitakyushu International Conference Center | Control Signal Extraction for Sequential Clock Gating Using Time Expansion of Sequential Circuits Tomoya Goto, Kohei Higuchi, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2015-4 |
Recently, clock gating is utilized as a method for reducing the dynamic power of LSI. Clock gating can be automatically... [more] |
VLD2015-4 pp.31-36 |
| VLD | 2015-03-03 16:15 |
Okinawa | Okinawa Seinen Kaikan | [Memorial Lecture]
A Bit-Write Reduction Method based on Error-Correcting Codes for Non-Volatile Memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-173 |
Non-volatile memory is superior to SRAM in terms of its high density and low leakage power but it consumes larger writ... [more] |
VLD2014-173 p.115 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 09:40 |
Oita | B-ConPlaza | Small-Sized Encoder/Decoder Circuit Design for Bit-Write Reduction Targeting Non-Volatile Memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-106 DC2014-60 |
Non-volatile memory has many advantages such as low leakage power and non-volatility. However, there are problems that ... [more] |
VLD2014-106 DC2014-60 pp.227-232 |
| CAS, SIP, MSS, VLD, SIS [detail] | 2014-07-11 13:40 |
Hokkaido | Hokkaido University | Write Reduction of Internal Registers for Non-volatile RISC Processors Tomoya Goto, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) CAS2014-40 VLD2014-49 SIP2014-61 MSS2014-40 SIS2014-40 |
Recently next-generation non-volatile memories based on MTJ (Magnetic Tunnel Junction) have been paid attention because ... [more] | CAS2014-40 VLD2014-49 SIP2014-61 MSS2014-40 SIS2014-40 pp.213-218 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 15:15 |
Kanagawa | Hiyoshi Campus, Keio University | A Reduction Method of Writing Operations to Non-volatile Memory by Keeping Data Difference for Low-Power Circuit Design Hiroyuki Shinohara, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) VLD2013-130 CPSY2013-101 RECONF2013-84 |
In order to reduce the power consumption of LSI, unnecessary parts should be powered off with fine granularity, and c... [more] |
VLD2013-130 CPSY2013-101 RECONF2013-84 pp.167-172 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 10:50 |
Kagoshima | Energy evaluation of writing reduction method for non-volatile memory Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-81 DC2013-47 |
Non-volatile memory has many advantages over SRAM, such as high density, low leakage power, and non-volatility. However... [more] |
VLD2013-81 DC2013-47 pp.141-146 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 11:15 |
Kagoshima | Power Reduction of Non-volatile Logic Circuits Using the Minimum Writing Power Cut-set of State Registers Yudai Itoi, Shinji Kimura (Waseda Univ.) VLD2013-82 DC2013-48 |
Recently, the next generation non-volatile memory/register using magnetic tunnel junction elements has been paid attenti... [more] | VLD2013-82 DC2013-48 pp.147-152 |
|
| SIP, CAS, MSS, VLD | 2013-07-12 09:00 |
Kumamoto | Kumamoto Univ. | Evaluation of energy consumption for two-level cache using Non-Volatile Memory for IL1 and UL2 caches Shota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa (Waseda Univ.), Tadahiko Sugibayashi (NEC) CAS2013-17 VLD2013-27 SIP2013-47 MSS2013-17 |
A non-volatile memory has advantages such as low leak energy and non-volatility compared with SRAM or DRAM has high leak... [more] | CAS2013-17 VLD2013-27 SIP2013-47 MSS2013-17 pp.89-94 |
| SIP, CAS, MSS, VLD | 2013-07-12 09:20 |
Kumamoto | Kumamoto Univ. | A non-volatile memory writing reduction method based on state encoding limiting maximum Hamming distance Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) CAS2013-18 VLD2013-28 SIP2013-48 MSS2013-18 |
Non-volatile memory has many advantages over SRAM, such as high density, low leakage power, and non-volatility. However... [more] |
CAS2013-18 VLD2013-28 SIP2013-48 MSS2013-18 pp.95-100 |
[Return to Top Page]