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Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF, VLD 2024-01-29
17:00		 Kanagawa AIRBIC Meeting Room 1-4
(Primary: On-site, Secondary: Online)		 Derivation of an Evaluation Chip Spec suitable for Tester and Data Analysis -- Toward comparative evaluation of latch-based and flip-flop-based circuits --
Tadaaki Tanimoto, Keizo Hiraga, Toshihiko Katou, Kazuhiro Bessho, Toshimasa Shimizu (Sony Semiconductor Solutions) VLD2023-90 RECONF2023-93		 As a synchronous logic circuit, it is often argued that latch-based circuits are superior to flip-flop circuits in terms... [more] VLD2023-90 RECONF2023-93
pp.59-64
RECONF, VLD 2024-01-29
17:25		 Kanagawa AIRBIC Meeting Room 1-4
(Primary: On-site, Secondary: Online)		 Comparison of latch-based circuit and flip-flop-based circuit in actual device
Kenji Takahashi, Tadaaki Tanimoto, Keizo Hiraga, Masayuki Hayashi, Takato Inoue, Kazuhiro Bessho, Toshimasa Shimizu (Sony Semiconductor Solutions) VLD2023-91 RECONF2023-94		 The comparison results of current consumption, maximum operating frequency (Fmax) characteristics and minimum operating ... [more] VLD2023-91 RECONF2023-94
pp.65-70
VLD, CPSY, RECONF, IPSJ-SLDM 2007-01-18
11:25		 Tokyo Keio Univ. Hiyoshi Campus Model Checking of Cycle Accurate Hardware Behavior Models with Instantaneous Communication
Hirohisa Fujita, Masahiko Hamada, Tadaaki Tanimoto, Akio Nakata, Teruo Higashino (Osaka Univ.) 		Wiring delay imposes a limitation on
increase of clock frequency.
Therefore, instantaneous communications
consuming ... [more]		 VLD2006-98 CPSY2006-69 RECONF2006-69
pp.25-30
VLD, ICD, DC, IPSJ-SLDM 2005-12-02
11:25		 Fukuoka Kitakyushu International Conference Center A Method for Allocating Bus Transfer and Task Execution Cycles Based on Scenarios
Seiji Yamaguchi, Tadaaki Tanimoto, Akio Nakata, Teruo Higashino (Osaka Univ.) 		In designing a bus system, it is important to derive a real-time constraint (the number of available cycles) for each ta... [more] VLD2005-80 ICD2005-175 DC2005-57
pp.25-30
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