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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ICD | 2024-04-12 14:55 |
Kanagawa | (Primary: On-site, Secondary: Online) |
[Invited Lecture]
遠端ビット線プリチャージとウィークビットトラッキング回路を用いて0.48 - 1.2V動作電圧範囲と27.6Mbit/mm^2の高集積密度を実現する3ナノメートルSRAM Yumito Aoyagi, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Koji Nii, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang (TSMC) |
[more] | |
| SDM, ICD, ITE-IST [detail] | 2018-08-08 13:15 |
Hokkaido | Hokkaido Univ., Graduate School of IST M Bldg., M151 | [Invited Lecture]
A Highly Symmetrical 10T 2-Read/Write Dual-port SRAM Bitcell Design In 28nm High-k/Metal-gate Planar Bulk CMOS Technology Yuichiro Ishii, Miki Tanaka, Makoto Yabuuchi, Yohei Sawada, Shinji Tanaka, Koji Nii (Renesas), Tien Yu Lu, Chun Hsien Huang, Shou Sian Chen, Yu Tse Kuo, Ching Cheng Lung, Osbert Cheng (UMC)  SDM2018-40 ICD2018-27 |
We propose a highly symmetrical 10T 2-read/write (2RW) dual-port (DP) SRAM bitcell in 28-nm high-k/metal-gate planar bul... [more] | SDM2018-40 ICD2018-27 pp.83-88 |
| ICD | 2018-04-20 10:45 |
Tokyo | [Invited Lecture]
A Dynamic Power Reduction in Synchronous 2RW 8T Dual-Port SRAM by Adjusting Wordline Pulse Timing with Same/Different Row Access Mode Yoshisato Yokoyama, Yuichiro Ishii, Haruyuki Okuda, Koji Nii (REL) ICD2018-9 |
(To be available after the conference date) [more] | ICD2018-9 pp.33-38 |
|
| ICD | 2017-04-21 10:25 |
Tokyo | [Invited Lecture]
A 6.05-Mb/mm2 16-nm FinFET Double Pumping 1W1R 2-port SRAM with 313ps Read Access Time Yohei Sawada, Makoto Yabuuchi, Masao Morimoto (REL), Toshiaki Sano (RSD), Yuichiro Ishii, Shinji Tanaka (REL), Miki Tanaka (RSD), Koji Nii (REL) ICD2017-12 |
[more] | ICD2017-12 pp.63-65 |
|
| ICD, CPM, ED, EID, EMD, MRIS, OME, SCE, SDM, QIT (Joint) [detail] |
2017-01-31 15:25 |
Hiroshima | Miyajima-Morino-Yado(Hiroshima) | A 5.92-Mb/mm2 28-nm Pseudo 2-Read/Write Dual-Port SRAM Using Double Pumping Circuitry Yuichiro Ishii, Makoto Yabuuchi, Yohei Sawada, Masao Morimoto, Yasumasa Tsukamoto (Renesas Electronics), Yuta Yoshida, Ken Shibata, Toshiaki Sano (Renesas System Design), Shinji Tanaka, Koji Nii (Renesas Electronics) EMD2016-86 MR2016-58 SCE2016-64 EID2016-65 ED2016-129 CPM2016-130 SDM2016-129 ICD2016-117 OME2016-98 |
We propose pseudo dual-port (DP) SRAM by using 6T single-port (SP) SRAM bitcell with double pumping circuitry, which ena... [more] | EMD2016-86 MR2016-58 SCE2016-64 EID2016-65 ED2016-129 CPM2016-130 SDM2016-129 ICD2016-117 OME2016-98 pp.87-92 |
| ICD | 2016-04-14 10:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
A Cost Effective Test Screening Method on 40-nm 4-Mb Embedded SRAM for Low-power MCU Yuta Yoshida (RSD), Yoshisato Yokoyama, Yuichiro Ishii (Renesas Electronics), Toshihiro Inada, Koji Tanaka, Miki Tanaka, Yoshiki Tsujihashi (RSD), Koji Nii (Renesas Electronics) ICD2016-1 |
An embedded single-port SRAM with cost effective test screening circuitry is demonstrated for low-power micr... [more] | ICD2016-1 pp.1-6 |
| SDM | 2016-01-28 14:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
2RW Dual-port SRAM Design Challenges in Advanced Technology Nodes Koji Nii, Makoto Yabuuchi (Renesas), Yoshisato Yokoyama (Renesas System Design), Yuichiro Ishii, Takeshi Okagaki, Masao Morimoto, Yasumasa Tsukamoto (Renesas), Koji Tanaka, Miki Tanaka (Renesas System Design), Shinji Tanaka (Renesas) SDM2015-125 |
[more] | SDM2015-125 pp.21-25 |
| ICD | 2015-04-16 13:25 |
Nagano | [Invited Lecture]
A 512-kb 1-GHz 28-nm Partially Write Assisted Dual-Port SRAM with Self Adjustable Negative Bias Bitline Shinji Tanaka (Renesas Electronics), Yuichiro Ishii, Makoto Yabuuchi (Renesas), Toshiaki Sano (Renesas System Design), Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Hirotoshi Sato (Renesas) ICD2015-2 |
[more] | ICD2015-2 pp.5-8 |
|
| ICD | 2015-04-16 13:50 |
Nagano | [Invited Lecture]
40 nm Dual-port and Two-port SRAMs for Automotive MCU Applications under the Wide Temperature Range of -40 to 170℃ with Test Screening Against Write Disturb Issues Yoshisato Yokoyama, Yuichiro Ishii, Tatsuya Fukuda, Yoshiki Tsujihashi, Atsushi Miyanishi (Renesas Electronics), Shinobu Asayama, Keiichi Maekawa, Kazutoshi Shiba (Renesas Semiconductor Manufacturing Corporation), Koji Nii (Renesas Electronics) ICD2015-3 |
(To be available after the conference date) [more] | ICD2015-3 pp.9-14 |
|
| ICD, SDM | 2014-08-05 10:50 |
Hokkaido | Hokkaido Univ., Multimedia Education Bldg. | 40nm ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU Yoshisato Yokoyama, Yuichiro Ishii, Hidemitsu Kojima, Atsushi Miyanishi, Yoshiki Tsujihashi, Shinobu Asayama, Kazutoshi Shiba, Koji Tanaka, Tatsuya Fukuda, Koji Nii, Kazumasa Yanagisawa (Renesas) SDM2014-74 ICD2014-43 |
(To be available after the conference date) [more] | SDM2014-74 ICD2014-43 pp.65-70 |
| SDM, ICD | 2013-08-02 09:50 |
Ishikawa | Kanazawa University | A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Yuichiro Ishii (Renesas Electronics), Tetsuya Matsumura (Nihon Univ.), Yoshio Matsuda (Kanazawa Univ.) SDM2013-76 ICD2013-58 |
[more] | SDM2013-76 ICD2013-58 pp.53-57 |
| ICD | 2012-04-24 11:15 |
Iwate | Seion-so, Tsunagi Hot Spring (Iwate) | [Invited Talk]
Write-/Read- Disturb Issues and Circuit Solutions Yuichiro Ishii, Yasumasa Tsukamoto, Koji Nii, Hidehiro Fujiwara, Makoto Yabuuchi, Koji Tanaka, Shinji Tanaka, Yasuhisa Shimazaki (Renesas Electronics) ICD2012-11 |
This paper describes some circuit techniques for an 8T dual-port (DP) SRAM to improve its minimum operating voltage agai... [more] | ICD2012-11 pp.55-60 |
| SDM, ICD | 2011-08-26 15:05 |
Toyama | Toyama kenminkaikan | A 28-nm dual-port SRAM macro with active bitline equalizing circuitry against write disturb issue Yuichiro Ishii, Hidehiro Fujiwara, Koji Nii (Renesas Electronics), Hideo Chigasaki, Osamu Kuromiya, Tsukasa Saiki (Renesas Design), Atsushi Miyanishi, Yuji Kihara (Renesas Electronics) SDM2011-92 ICD2011-60 |
We propose circuit techniques for an 8T dual-port (DP) SRAM to improve its minimum operating voltage (Vddmin). Active bi... [more] | SDM2011-92 ICD2011-60 pp.109-114 |
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