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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS, ISEC, SITE, ICSS, EMM, IPSJ-CSEC, IPSJ-SPT [detail] | 2018-07-26 14:10 |
Hokkaido | Sapporo Convention Center | Compensation of Temperature Induced Flipping-Bits in CMOS SRAM PUF by NMOS Body-Bias Xuanhao Zhang, Xiang Chen, Hanfeng Sun, Hirofumi Shinohara (Waseda Univ.)  ISEC2018-41 SITE2018-33 HWS2018-38 ICSS2018-44 EMM2018-40 |
PUF suffers from flipping-bits caused by temperature changes which degrade the stability of output. This paper proposes ... [more] | ISEC2018-41 SITE2018-33 HWS2018-38 ICSS2018-44 EMM2018-40 pp.333-336 |
| DC | 2015-06-16 14:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A test data reduction method based on scan slice on BAST Makoto Nishikiori, Hiroshi Yamazaki, Toshinori Hosokawa, Masayuki Arai (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2015-16 |
BAST is one of techniques to reduce the amount of test data while maintaining high test quality by combining built-in se... [more] | DC2015-16 pp.1-6 |
| DC | 2014-02-10 15:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A reduction method of shift data volume on BAST Marika Tanaka, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ), Masayuki Arai (Nihon Univ) DC2013-87 |
BAST is one of techniques to reduce the amount of test data while maintaining the high test quality using built-in self ... [more] | DC2013-87 pp.49-54 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 14:10 |
Kagoshima | An inverter block construction method to reduce test data volume on BAST Marika Tanaka, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ), Masayuki Arai (Nihon Univ), Michinobu Nakao (Yomiuri Institute) VLD2013-85 DC2013-51 |
BAST is one of technique to reduce the amount of test data while maintaining the high test quality using built-in self t... [more] | VLD2013-85 DC2013-51 pp.171-176 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-29 09:50 |
Miyazaki | NewWelCity Miyazaki | A Scan Chain Construction Method to Reduce Test Data Volume on BAST Yun Chen, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) VLD2011-73 DC2011-49 |
BAST is one of techniques which are combined ATPG and BIST to reduce the amount of test data while maintaining the high ... [more] | VLD2011-73 DC2011-49 pp.127-132 |
| DC | 2010-06-25 15:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A test pattern matching method on BAST architecture using don't care identification for the detection of random pattern resistant faults Yun Chen, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) DC2010-11 |
BAST is one of techniques which are combined ATPG and BIST to reduce the amount of test data while maintaining the high ... [more] | DC2010-11 pp.19-24 |
| DC | 2009-02-16 15:20 |
Tokyo | A Method to Increase the Number of Don't care based on Easy- To-Detected Faults
-- Application for BAST Architecture -- LingLing Wan (Graduate Schoo of Nihon Univ.), Motohiro Wakazono (Graduate School of Nihon Univ.), Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) DC2008-76 |
The BIST Aided Scan Test (BAST) is a technique that combines the automatic test pattern generator (ATPG) and the Built-... [more] |
DC2008-76 pp.49-54 |
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