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Committee Date Time Place Paper Title / Authors Abstract Paper #
CPSY, DC, IPSJ-ARC [detail] 2022-10-12
14:00		 Niigata Yuzawa Toei Hotel
(Primary: On-site, Secondary: Online)		 A Don't Care Filling Algorithm of Control Signals for Concurrent Testing
Xu Haofeng, Hosokawa Toshinori (Nihon Univ.), Yoshimura Masayoshi (KSU), Arai Masayuki (Nihon Univ.) CPSY2022-24 DC2022-24		 In recent years, with the increase in test cost for VLSIs, it has been important to reduce the number of test patterns. ... [more] CPSY2022-24 DC2022-24
pp.37-42
DC 2018-02-20
09:55		 Tokyo Kikai-Shinko-Kaikan Bldg. A Test Register Assignment Method for Operational Units to Reduce the Number of Test Patterns for Transition Faults Using Controller Augmentation
Yuki Takeuchi, Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2017-78		 It is required to reduce the number of test patterns to reduce test cost for VLSIs. Especially, design-for-testability m... [more] DC2017-78
pp.7-12
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]		 2017-11-06
15:20		 Kumamoto Kumamoto-Kenminkouryukan Parea A Test Register Assignment Method to Reduce the Number of Test Patterns at Register Transfer Level Using Controller Augmentation
Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ) VLD2017-37 DC2017-43		 Recently, it is very important to reduce the number of test patterns by using design-for-testability (DFT) with the incr... [more] VLD2017-37 DC2017-43
pp.61-66
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2010-12-01
11:25		 Fukuoka Kyushu University A Sequential Test Generation Method and a Binding Method for Testability Using Behavioral Description
Ryoichi Inoue, Hiroaki Fujiwara, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (NAIST) VLD2010-76 DC2010-43		 Although many works on test generation algorithms for sequential circuits have been reported so far, it is still very ha... [more] VLD2010-76 DC2010-43
pp.143-148
VLD, CAS, SIP 2008-06-27
10:00		 Hokkaido Hokkaido Univ. On the Test Environment Generation Problem Using Assignment Decision Diagrams
Yuki Shimizu (NAIST), Chia Yee Ooi (UTM), Hideo Fujiwara (NAIST) CAS2008-22 VLD2008-35 SIP2008-56		 In this paper, we consider a problem of test environment generation for functional register-transfer level (RTL) circuit... [more] CAS2008-22 VLD2008-35 SIP2008-56
pp.19-24
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