IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 107, Number 506

VLSI Design Technologies

Workshop Date : 2008-03-05 / Issue Date : 2008-02-27

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Table of contents

VLD2007-137
Automatic synthesis and verification of practical protocol transducer based on product graph exploration
Yuji Ishikawa (Univ. of Tokyo), Satoshi Komatsu, Masahiro Fujita (VDEC, Univ. of Tokyo)
pp. 1 - 6

VLD2007-138
Task Scheduling Technique for Mitigating SEU Vulnerability of Heterogeneous Multiprocessor Systems
Makoto Sugihara (TUT)
pp. 7 - 12

VLD2007-139
An accurate Algorithm for RTL Power Macro-modeling
Masaaki Ohtsuki, Masato Kawai, Masahiro Fukui (Ritsumeikan Univ.)
pp. 13 - 18

VLD2007-140
Minimizing Minimum Delay Compensations in Datapath Synthesis
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST)
pp. 19 - 24

VLD2007-141
An Energy-efficent ASIP Synthesis Method Based on Reducing Bit-width of Instruction Memory
Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)
pp. 25 - 30

VLD2007-142
Analog Floorplan with Soft-Module Configuration
Kentarou Murata, Kazuya Sasaki, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu)
pp. 31 - 36

VLD2007-143
MOS Analog Module Generation
Akio Fujii, Takehiko Matsuo, Toru Fujimura, Bo Yang, Shigetoshi Nakatake (Univ. of Kitakyushu)
pp. 37 - 42

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan