IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 108, Number 248

Dependable Computing

Workshop Date : 2008-10-20 / Issue Date : 2008-10-13

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Table of contents

DC2008-22
Fault-Tolerant Multilayer Neural Networks for Multiple Weight-and-Neuron-Fault
Kazuhiro Nishimura (Polytech Univ.), Masato Ootsu (JP Network), Tadayoshi Horita (Polytech Univ.), Itsuo Takanami (Ichinoseki kousen (former))
pp. 1 - 6

DC2008-23
An implementation of a fault-tolerant 2D systolic array on an FPGA and its evaluation
Tadayoshi Horita (Polytechnic Univ.), Itsuo Takanami (Ichinoseki National College of Tech. in former times)
pp. 7 - 12

DC2008-24
A Note on Evaluation Techniques for Fault Tolerant Processor
Satoshi Fukumoto, Masayuki Arai, Kazuhiko Iwasaki (Tokyo Metropolitan Univ.)
pp. 13 - 16

DC2008-25
A Power Optimization Method for Quorum Systems
Munetoshi Ishikawa, Koji Hasebe (Tsukuba Univ.), Akiyoshi Sugiki (JST), Takahiro Shinagawa (Tsukuba Univ.), Kazuhiko Kato (Tsukuba Univ., JST)
pp. 17 - 22

DC2008-26
Feature Interaction Verification Using Model Checking with Interpolation
Takafumi Matsuo, Tatsuhiro Tsuchiya, Tohru Kikuno (Osaka Univ.)
pp. 23 - 28

DC2008-27
[Invited Talk] DSN2008 Report The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks
Nobuyasu Kanekawa (Hitachi)
pp. 29 - 32

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan