Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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RECONF2008-38
An emulation experiment of an inversion/non-inversion dynamic optical reconfiguration architecture
Shinichi Kato, Minoru Watanabe (Shizuoka Univ.)
pp. 1 - 4
RECONF2008-39
Assembly accuracy of a holographic memory in an optically reconfigurable gate array
Hironobu Morita, Minoru Watanabe (Shizuoka Univ.)
pp. 5 - 8
RECONF2008-40
Preliminary Evaluations of SMA: A Massive Array of Low-Power Reconfigurable Processors
Hideharu Amano (Keio Univ.), Kyundong Kim (Tokyo Univ.), Hiroki Matsutani, Vasutan Tunbungheng, Yoshihiro Yasuda (Keio Univ.), Masaaki Kondo (The University of Electro-Communications), Hiroshi Nakamura (Tokyo Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.)
pp. 9 - 14
RECONF2008-41
A Method of Processing Data-Parallel Tasks on Multi-Context Reconfigurable Processor
Koichi Araki, Yukinori Sato, Yasushi Inoguchi (Japan Advanced Institute of Science and Technology)
pp. 15 - 20
RECONF2008-42
A Study of Local Interconnect Architecture for Variable Grain Logic Cell
Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 21 - 26
RECONF2008-43
Adaptive routing of the 2-D torus network based on a Turn model
Kazuya Matoyama, Yasuyuki Miura, Shigeyoshi Watanabe (Shonan Institute of Technology)
pp. 27 - 32
RECONF2008-44
Hardware Implementation Costs of Adaptive Routing in the Hierarchical Interconnection Network
Masahiro Kaneko, Yasuyuki Miura, Shigeyoshi Watanabe (Shonan Institute of Technology)
pp. 33 - 38
RECONF2008-45
Soft Error Mitigation Techniques for FPGA Switch Matrices
Yuki Kou, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima (Nara Institute of Science and Technology)
pp. 39 - 44
RECONF2008-46
Inter-FPGA communication mechanism of FPGA-array for high-performance difference scheme computation
Wang Luzhou, Kentaro Sano, Yoshiaki Hatsuda, Satoru Yamamoto (Tohoku Univ.)
pp. 45 - 48
RECONF2008-47
[Invited Talk]
The End of Moore`s Law and the Future of Computing Systems, Probably
Krishna V. Palem (Rice Univ.)
p. 49
RECONF2008-48
[Invited Talk]
C-based Programmable-HW Core "STP Engine": Current Status and the Future
Masato Motomura (NEC Electronics)
pp. 51 - 56
RECONF2008-49
On Programmable Two-Variable Numerical Function Generators
Shinobu Nagayama (Hiroshima City Univ.), Tsutomu Sasao (Kyushu Institute of Technology), Jon T. Butler (Naval Postgraduate School)
pp. 57 - 62
RECONF2008-50
An Adaptive Pattern Recognition hardware with On-chip Dynamic and Partial Reconfiguration
Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga (Tsukuba Univ.), Kyrre Glette, Jim Toressen (Oslo Univ.)
pp. 63 - 68
RECONF2008-51
A Novel Network Optimization Method using On-Chip Virtual Network on Dynamically Reconfigurable Processor DAPDNA-2
Shan Gao, Taku Kihara, Sho Shimizu, Yutaka Arakawa, Naoaki Yamanaka (Keio University), Kosuke Shiba (IPFlex Inc)
pp. 69 - 74
RECONF2008-52
An improvement of Black-Diamond compiler for representing target dynamically reconfigurable architecture
Vasutan Tunbunheng, Hideharu Amano (Keio Univ.)
pp. 75 - 80
RECONF2008-53
The Experiment of Automatic circuit generation for image processing using extended C code on DRP
-- DFC, the Language of Hardware generation for DAPDNA - its issue and solution --
Kazuo Yamada, Takao Naito (Fuji Xerox), Mitsumasa Yoshimura, Jiro Iwai (IPFlex)
pp. 81 - 86
RECONF2008-54
Development of Side-channel Attack Standard Evaluation BOard and Tool
Yohei Hori, Toshihiro Katashita, Hirofumi Sakane, Kenji Toda, Akashi Satoh (National Institute of Advanced Industrial Science and Technology), Hideki Imai (Chuo Univ.)
pp. 87 - 92
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.