IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 109, Number 198

Reconfigurable Systems

Workshop Date : 2009-09-17 - 2009-09-18 / Issue Date : 2009-09-10

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Table of contents

RECONF2009-19
Rea-time detection of rotated patterns using FPGA
Yoshifumi Tanida, Tsutomu Maruyama (Tsukuba Univ.)
pp. 1 - 6

RECONF2009-20
Component Labeling on the FPGA using Few Logic Elements
Yasuaki Ito, Koji Nakano (Hiroshima Univ.)
pp. 7 - 12

RECONF2009-21
Performance Evaluation of Levenshtein-Distance Computation on One-Dimensional FPGA Array Cube
Masato Yoshimi, Mitsunori Miki (Doshisha Univ.), Yuri Nishikawa, Akihiro Shitara, Hideharu Amano (Keio Univ.), Oskar Mencer (Imperial College London)
pp. 13 - 18

RECONF2009-22
FPGA implementation and accuracy evaluation of a power-supply voltage control circuit
Masato Soejima, Junya Sakemi, Yuichiro Shibata, Fujio Kurokawa, Tsuyoshi Hamada, Tomonari Masada, Kiyoshi Oguri (Nagasaki Univ)
pp. 19 - 24

RECONF2009-23
Low-power oriented clustering and placement tools using routability for FPGAs
Shinya Imaizumi, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 25 - 30

RECONF2009-24
An analysis of frequency in the use LUT logic functions based on P-equivalence class
Masaki Shintani, Kota Kato, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 31 - 36

RECONF2009-25
Design and Fabrication of Flex Power FPGA with Power Reconfigurability
Masakazu Hioki (AIST), Takashi Kawanami (Kanazawa Inst. of Tech.), Yohei Matsumoto (AIST), Toshiyuki Tsutsumi (Meiji Univ.), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST)
pp. 37 - 42

RECONF2009-26
Leakage Power Reduction of a Dynamically Reconfigurable Processors with Deal Vth cells
Hideharu Amano, Keiichiro Hirai, Toru Sano, Masaru Kato, Yoshiki Saito (Keio Univ.)
pp. 43 - 48

RECONF2009-27
[Invited Talk] YAWARA: A Self-Optimizing Computer System Project
Takanobu Baba, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.)
pp. 49 - 54

RECONF2009-28
A Proposal for a Method to Generate Optimized Dataflow for Reconfigurable Processor DS-HIE Based on Bit Serial Operation
Yasuhiro Nishinaga, Ken'ichi Umeda, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.)
pp. 55 - 60

RECONF2009-29
Consideration of Data Transfer Unit in Reconfigurable Processor DS-HIE
Ken'ichi Umeda, Yasuhiro Nishinaga, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ)
pp. 61 - 66

RECONF2009-30
Comparison and Evaluation of Application Implementation Methods for Dynamically Reconfigurable Processor DAPDNA-2
Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ)
pp. 67 - 72

RECONF2009-31
A Study of Scalable Prototyping System with Small-sized FPGAs
Shimpei Watanabe, Shinya Takamaeda, Ken Kyou (Tokyo Inst. of Tech), Takefumi Miyoshi (Tokyo Inst. of Tech/JST), Kenji Kise (Tokyo Inst. of Tech)
pp. 73 - 78

RECONF2009-32
An FPGA-based Tiny Processing System for Small Embedded System and Education
Koji Nakano, Yasuaki Ito, Kensuke Kawakami, Koji Shigemoto (Hiroshima Univ)
pp. 79 - 84

RECONF2009-33
A Study of Topology-adaptive Network-on-Chip for Many-Core SoC
Hiroshi Kadota (Kyushu Univ.), Akiyoshi Wakatani (Konan Univ.)
pp. 85 - 90

RECONF2009-34
Packet Capturing and Routing Functions on a Network Testbed GtrcNET-10p3
Yuetsu Kodama, Ryousei Takano, Fumihiro Okazaki, Tomohiro Kudoh (AIST)
pp. 91 - 96

RECONF2009-35
High-density Implementation for Reconfigurable Device MPLD
Hiroaki Toguchi, Masanori Asaeda, Yutaro Oda, Naoki Hirakawa, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.), Masayuki Sato, Takashi Ishiguro (TAIYO YUDEN CO.LTD)
pp. 97 - 102

RECONF2009-36
An Asynchronous FPGA Using LEDR/4-Phase-Dual-Rail Protocol Converters
Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.)
pp. 103 - 108

RECONF2009-37
A writer system not using an imaging lens for 4-context programmable optically reconfigurable gate arrays
Shinya Kubota, Minoru Watanabe (Shizuoka Univ.)
pp. 109 - 112

RECONF2009-38
FPGA-based Stream Computation for HPC -- Designing and Evaluating a Scalable Pipeline-Module for 2D Jacobi Computation --
Kentaro Sano, Yoshiaki Hatsuda, Yasuhiro Otsubo, Satoru Yamamoto (Tohoku Univ.)
pp. 113 - 118

RECONF2009-39
A study of an Implementation Method of a Mathematical Function in Reconfigurable Accelerator with High-Precision Floating Point Arithmetic
Yuki Yoshioka, Tomoyuki Kawamoto, Taiga Ban, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ)
pp. 119 - 124

RECONF2009-40
An FPGA-based Architecture for Verifying Collatz Conjecture
Yasuaki Ito, Koji Nakano (Hiroshima Univ.)
pp. 125 - 130

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan