IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

Dependable Computing

Workshop Date : 2009-06-19 / Issue Date : 2009-06-12

DC2009-10
Design method of easily testable parallel prefix adders
Hidetoshi Suzuki, Naofumi Takagi (Nagoya Univ)
pp. 1 - 6

DC2009-11
Note on Yield and Area Trade-offs for MBIST in SoC
Masayuki Arai, Tatsuro Endo, Kazuhiko Iwasaki (Tokyo Metro. Univ.), Michinobu Nakao, Iwao Suzuki (Renesas Tech Corp.)
pp. 7 - 12

DC2009-12
A Test Generation Algorithm Based on 5-valued Logic for Threshold Testing
Nobukazu Izumi, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 13 - 18

DC2009-13
Diagnositc Test Generation for Transition Faults Using a Stuck-at ATPG Tool
Yoshinobu Higami, Yosuke Kurose, Satoshi Ohno, Hironori Yamaoka, Hiroshi Takahashi (Ehime Univ.), Yoshihiro Simizu, Takashi Aikyo (STARC), Yuzo Takamatsu (Ehime Univ.)
pp. 19 - 24

DC2009-14
[Invited Talk] High-level Design for Test Tools & Industrial Design Flows
Chouki Aktouf (DeFacTo)
pp. 25 - 28

DC2009-15
Power & Noise Aware Test Utilizing Preliminary Estimation
Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo (STARC)
pp. 29 - 30

DC2009-16
*
Koichiro Noguchi, Koichi Nose (NEC Corp.), Toshinobu Ono (NEC Electronics Corp.), Masayuki Mizuno (NEC Corp.)
pp. 31 - 34

DC2009-17
Case study: Fault diagnosis for detecting systematic fault
Hiroshi Yamamoto, Hiroki Wada, Toru Ogushi, Michinobu Nakao (Renesas Tech. Corp.)
p. 35

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan