IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 110, Number 315

Integrated Circuits and Devices

Workshop Date : 2010-11-29 - 2010-11-30 / Issue Date : 2010-11-22

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Table of contents

ICD2010-83
Evaluation of frequency components of power noise in CMOS digital LSI
Kumpei Yoshikawa, Hiroshi Matsumoto, Yuta Sasaki (Kobe Univ.), Makoto Nagata (Kobe Univ./CREST-JST)
pp. 1 - 6

ICD2010-84
Evaluation of on-chip power noise generation and injection in SRAM core
Takuya Sawada, Taku Toshikawa, Tsubasa Masui (Kobe Univ.), Makoto Nagata (Kobe Univ./CREST-JST)
pp. 7 - 12

ICD2010-85
A Consideration of Substrate Noise Sensitivity of Analog Elements
Satoshi Takaya, Yoji Bando, Takashi Hasegawa (Kobe Univ.), Toru Ohkawa, Masaaki Souda, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami (MIRAI-Selete), Makoto Nagata (Kobe Univ.)
pp. 13 - 17

ICD2010-86
Evaluation of Signal-Integrity Improvement Capability of the Segmental Transmission Line -- In Its Application to Lines Including Inductances --
Hiroki Shimada, Shohei Akita, Masami Ishiguro, Moritoshi Yasunaga, Noriyuki Aibe (Univ. of Tsukuba), Ikuo Yoshihara (Univ. of Miyazaki)
pp. 19 - 24

ICD2010-87
[Invited Talk] Problems of on-chip interconnection and optical interconnection
Shin Yokoyama, Yoshiteru Amemiya (Hiroshima Univ.)
pp. 25 - 30

ICD2010-88
[Invited Talk] Present Status and Target Issue of LSI-Chip Optical Interconnection
Keishi Ohashi (MIRAI-Selete/NEC), Tohru Mogami (MIRAI-Selete)
pp. 31 - 36

ICD2010-89
[Invited Talk] Research Trends and Future Directions for Optical Interconnects Technologies
Toshiki Sugawara, Yasunobu Matsuoka, Shin-ichi Saito, Naoki Matsushima, Shinji Tsuji (Hitachi)
pp. 37 - 42

ICD2010-90
17 Gb/s VCSEL Driver Using Double-Pulse Asymmetric Emphasis Technique for Optical Interconnection
Takaya Taniguchi, Kiichi Yamashita, Kenichi Ohhata (Kagoshima Univ.), Norio Chujo, Toru Yazaki (Hitachi)
pp. 43 - 47

ICD2010-91
Improvement and Evaluation of via programmable structured ASIC VPEX
Ryohei Hori, Tatsuya Kitamori, Taisuke Ueoka (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.)
pp. 49 - 54

ICD2010-92
An estimation of a dynamic partial reconfiguration capability of a dynamic optically reconfigurable gate array
Amarjargal Gundjalam, Minoru Watanabe (Shizuoka Univ.)
pp. 55 - 60

ICD2010-93
[Invited Talk] System Performance Improvement Expected for 3D LSI Chip Stacking Integration Technology
Masahiro Aoyagi (AIST)
pp. 61 - 65

ICD2010-94
[Invited Talk] A wafer-level system integration technology for heterogeneous devices with pseudo-SoC
Hiroshi Yamada, Yutaka Onozuka, Atsuko Iida, Kazuhiko Itaya, Hideyuki Funaki (Toshiba R&D Center)
pp. 67 - 72

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan