IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

VLSI Design Technologies

Workshop Date : 2010-11-29 - 2010-12-01 / Issue Date : 2010-11-22

VLD2010-57
An Approach to Translate from Mathematical to Electronic Descriptions of Image Processing Algorithm for ITS
Yukio Fujita, Masanori Tsuzuki, Yoshiya Sugita, Masahiro Fukui (Ritsumeikan Univ.)
pp. 1 - 6

VLD2010-58
Rapid SoC Prototyping Based on Virtual Multi-Processor Model
Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo/JST)
pp. 7 - 12

VLD2010-59
A Scalable Heuristic for Incremental High-Level Synthesis
Shohei Ono (Univ. Tokyo), Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo/JST)
pp. 13 - 18

VLD2010-60
A Binding Algorithm for Multi-cycle Fault Tolerant Datapaths
Hayato Henmi, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 25 - 30

VLD2010-61
Evaluation of Multi-Cycle Test with Partial Observation in Scan BIST Structure
Hisato Yamaguchi, Makoto Matsuzono, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech./JST)
pp. 31 - 36

VLD2010-62
A decision method of target detected pseudo primary outputs on Low-capture-swithing-activity test generation
Yang Shen, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ)
pp. 37 - 42

VLD2010-63
Experimental Evaluation of Built-in Test Pattern Generation with Image Decoders
Yuka Iwamoto, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
pp. 43 - 48

VLD2010-64
Speeding-up Exact and Fast L1 Cache Configuration Simulation based on FIFO Replacement Policy
Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.)
pp. 55 - 60

VLD2010-65
Energy Aware Instruction Scheduling for Fine Grained Power Gated VLIW Processors
Ittetsu Taniguchi, Mitsuya Uchida, Hiroyuki Tomiyama, Masahiro Fukui (Ritsumeikan Univ.)
pp. 61 - 66

VLD2010-66
A study of high-performance asynchronous network-on-chip focused on bias of packets transfer routes
Satoshi Takeyasu, Masashi Imai, Hiroshi Nakamura (Tokyo Univ.)
pp. 67 - 72

VLD2010-67
FPGA design and test methodology for communication frame processinng
Ritsu Kusaba, Kenji Kawai, Sadayuki Yasuda, Satoshi Shigematsu, Mamoru Nakanishi, Masami Urano (NTT)
pp. 73 - 78

VLD2010-68
Evaluation of FPGA Implementation Techniques for High-Performance SoC Prototypes
Hideo Tanida (Univ. of Tokyo), Hiroaki Yoshida, Masahiro Fujita (Univ. of Tokyo/JST)
pp. 79 - 84

VLD2010-69
[Invited Talk] Paper Writing Guide for International Conferences -- Implications in VLSI design methodology field --
Masanori Hashimoto (Osaka Univ.)
p. 91

VLD2010-70
Accurate Delay Analysis Method of Power-Gated Circuit
Seidai Takeda, Kim Kyundong, Hiroshi Nakamura (Univ. of Tokyo), Kimiyoshi Usami (Shibaura Inst. of Tech.)
pp. 93 - 98

VLD2010-71
[Invited Talk] Photonic-electronic Convergence Technology Based on Silicon -- Integration of photomic and electric circuits utilizing Siliconphotonics --
Seiichi Itabashi, Tai Tsuchizawa, Koji Yamada, Toshifumi Watanabe, Hiroyuki Shinojima, Hidetaka Nishi, Rei Takahashi (NTT Corp.), Kazumi Wada, Yasuhiko Ishikawa (Univ. of Tokyo.)
pp. 105 - 106

VLD2010-72
SREEP: A Tool for Secure Scan Design Using Shift Register Equivalents
Katsuya Fujiwara (Akita Univ.), Hideo Fujiwara (NAIST), Hideo Tamamoto (Akita Univ.)
pp. 107 - 112

VLD2010-73
Fault-Injection using Virtualized Environment for Validating Automotive Systems
Yasuhiro Ito (Hitachi.), Yohei Nakata, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST), Yasuo Sugure, Shigeru Oho (Hitachi.)
pp. 119 - 123

VLD2010-74
Evaluation and Verification of Dependable Processor Architecture Using System-Level Fault-Injection Scheme
Yohei Nakata (Kobe Univ.), Yasuhiro Ito, Yasuo Sugure, Shigeru Oho (Hitachi Ltd.), Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST)
pp. 125 - 130

VLD2010-75
ILP Approach to Extended Ordered Coloring for Skew Adjustability-Aware Resource Binding
Mineo Kaneko (JAIST)
pp. 131 - 136

VLD2010-76
A Sequential Test Generation Method and a Binding Method for Testability Using Behavioral Description
Ryoichi Inoue, Hiroaki Fujiwara, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (NAIST)
pp. 143 - 148

VLD2010-77
Adjacent Insertion and Its Effectiveness in Code-Based 3-D Placement
Shin Uesugi, Mineo Kaneko (JAIST)
pp. 149 - 154

VLD2010-78
On pruning rules in exact algorithms for the minimum rectilinear Steiner arborescence problem
Masayuki Nagase, Toshihiko Takahashi (Niigat Univ.)
pp. 155 - 159

VLD2010-79
Analysis of Channel Decomposition for Structured Analog Layout and Low-power Applications
Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu)
pp. 161 - 166

VLD2010-80
Develop A Clock Tree Generator into Open-source CAD System.
Takuya Higuchi, Jun'ichiro Ogane, Naohiko Shimizu (Tokai Univ.)
pp. 167 - 172

VLD2010-81
Optimal adder architecture in ultra low voltage domain
Nao Konishi, Masaru Kudo, Kimiyoshi Usami (Shibaura Inst. Tech.)
pp. 173 - 178

VLD2010-82
A proposal for VLSI model for evaluation of rush current by power gating
Hiroto Yamaguchi, Junki Miyajima, Tomohiko Sumi, Masahiro Fukui (Ritsumeikan Univ.), Shuji Tsukiyama (Chuo Univ.)
pp. 179 - 184

VLD2010-83
Sharing of Clock Gating Modules under Multi-Stage Clock Gating Control
Xin Man (Waseda Univ.), Takashi Horiyama (Saitama Univ.), Tomoo Kimura, Koji Kai (Panasonic), Shinji Kimura (Waseda Univ.)
pp. 185 - 190

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan