Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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RECONF2010-1
FPGA Implementation of Fast Proportional Digital PID Control for DC-DC Converters
Kazuma Hamawaki, Yuki Maeda, Masato Soejima, Yuichiro Shibata, Kiyoshi Oguri, Fujio Kurokawa (Nagasaki Univ.)
pp. 1 - 6
RECONF2010-2
An FPGA implementation of Full-search variable block size motion Estimation
Shuichi Asano, Zhi Shun Zheng, Tsutomu Maruyama (Univ. of Tsukuba)
pp. 7 - 12
RECONF2010-3
Real-time processing of contrast limited adaptive histogram equalization on FPGA
Kentaro Kokufuta, Tsutomu Maruyama (Univ. of Tsukuba)
pp. 13 - 18
RECONF2010-4
A study on multicore designed MuCCRA3 : dynamically reconfigurable processor array
Eiichi Sasaki, Yoshiki Saito, Masayuki Kimura, Hideharu Amano (Keio Univ.)
pp. 19 - 24
RECONF2010-5
First Prototype Chip of a Non-Volatile Reconfigurable Logic using FeRAM Cells
Masahiro Koga, Masahiro Iida, Motoki Amagasaki (Kumamoto Univ.), Yoshinobu Ichida, Mitsuro Saji, Jun Iida (ROHM), Toshinori Sueyoshi (Kumamoto Univ.)
pp. 25 - 30
RECONF2010-6
Digit-Serial Floating Point Unit for High Precision Scientific Computation Engine
Kazuya Tanigawa, Taiga Ban, Tetsuo Hironaka (Hiroshima City Univ.)
pp. 31 - 36
RECONF2010-7
A Case Study of Evaluation Technique for Soft Error Tolerance on SRAMs-based FPGAs.
Tsuyoshi Kimura, Noritaka Kai, Yoshiaki Tsutsumi, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 37 - 42
RECONF2010-8
A datapath classification method for efficient arithmetic pipeline combining on FPGAs
Yui Ogawa, Tomonori Ooya (Nagasaki Univ.), Yasunori Osana (Seikei Univ.), Masato Yoshimi (Doshisha Univ.), Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano (Keio Univ.), Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)
pp. 43 - 48
RECONF2010-9
[Invited Talk]
Stream processing bring out performance of wired logic
Kiyoshi Oguri (Nagasaki Univ.)
pp. 49 - 50
RECONF2010-10
Detecting patterns in various size and angle using FPGA
Masayuki Suzuki, Yoshifumi Tanida, Tsutomu Maruyama (Univ. of Tsukuba)
pp. 51 - 56
RECONF2010-11
An FPGA Implementation of Tracking Control System with Vibration Control
Yasuaki Tezuka, Shuichi Ichikawa, Yoshiyuki Noda (TUT)
pp. 57 - 62
RECONF2010-12
Software-Hardware Communication and Remote Call on a PC-FPGA Hybrid Cluster
Masaki Kohata, Akira Uejima, Ryo Ozaki (Okayama Univ. of Sci.)
pp. 63 - 68
RECONF2010-13
GALS Design for Scalable Array Processors Operating on Multiple FPGAs
Wang Luzhou, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.)
pp. 69 - 74
RECONF2010-14
Evaluation using Multiple Different Applications of OS for an FPGA-based Reconfigurable System
Akira Kojima, Kazuya Tokunaga, Tetsuo Hironaka (Hiroshima City Univ.)
pp. 75 - 80
RECONF2010-15
An Efficient Implementation of Exhaustive Verification of the Collatz Conjecture using DSP48E blocks of Xilinx Virtex-5 FPGAs
Yasuaki Ito, Koji Nakano (Hiroshima Univ.)
pp. 81 - 86
RECONF2010-16
Implementation of Arithmetic Pipeline on FLOPS-2D:Multi-FPGA Platform
Hirokazu Morishita, Kenta Inakagata (Keio Univ.), Yasunori Osana (Seikei Univ.), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.)
pp. 87 - 92
RECONF2010-17
A translational system using dynamic reconfigurable processor
Kei Kinoshita, Daisuke Takano, Tomoyuki Okamura, Tetsuhiko Yao, Yoshiki Yamaguchi (Univ. of Tsukuba)
pp. 93 - 98
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.