Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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ICD2012-1
[Invited Talk]
A 19nm 112.8mm2 64Gb Multi-level(2bit/cell) Flash Memory with 400Mb/s/pin 1.8V Toggle Mode Interface
Noboru Shibata, Kazushige Kanda, Toshiki Hisada, Katsuaki Isobe, Manabu Sato, Yuui Shimizu, Takahiro Shimizu, Takahiro Sugimoto, Tomohiro Kobayashi, Kazuko Inuzuka, Naoaki Kanagawa, Yasuyuki Kajitani, Takeshi Ogawa, Jiyun Nakai (Toshiba), Teruhiko Kamei (SanDisk)
pp. 1 - 5
ICD2012-2
[Invited Talk]
128Gb 3-Bit Per Cell NAND Flash Memory on 19nm Technology with 18MB/s Write Rate
Teruhiko Kamei, Yan Li, Seungpil Lee, Ken Oowada, Hao Nguyen, Qui Nguyen, Nima Mokhlesi, Cynthia Hsu, Jason Li, Venky Ramachandra, Masaaki Higashitani, Tuan Pham, Mitsuyuki Watanabe (SanDisk), Mitsuaki Honma, Yoshihisa Watanabe (Toshiba)
pp. 7 - 12
ICD2012-3
[Invited Talk]
An 8Mb Multi-Layered Cross-Point ReRAM Macro with 443MB/s Write Throughput
Akifumi Kawahara, Ryotaro Azuma, Yuuichirou Ikeda, Ken Kawai, Yoshikazu Katoh, Yukio Hayakawa, Kiyotaka Tsuji, Shinichi Yoneda, Atsushi Himeno, Kazuhiko Shimakawa, Takeshi Takagi, Takumi Mikawa, Kunitoshi Aono (Panasonic)
pp. 13 - 18
ICD2012-4
[Invited Talk]
Dependable SSD design
-- The Issue for Enabling High Capacity Storage Device with Semiconductor --
Hiroshi Sukegawa (TOSHIBA)
pp. 19 - 21
ICD2012-5
[Invited Talk]
Over-10x-Extended-Lifetime 76%-Reduced-Error Solid-State Drives (SSDs) with Error-Prediction LDPC Architecture and Error-Recovery Scheme
Shuhei Tanakamaru, Yuki Yanagihara, Ken Takeuchi (Univ. Tokyo)
pp. 23 - 28
ICD2012-6
[Panel Discussion]
Thinking of Reconstruction of Japan Semiconductor Indutory in Iwate
Shinji Miyano (STARC), Atsushi Sasaki (Iwate Prefecture), Motoyuki Oishi (Nihon Keizai Shimbun,Inc.), Shoun Matsunaga (Tohoku University), Ken Takeuchi (Chuo Univ.), Hiroshi Sukegawa (Toshiba)
p. 29
ICD2012-7
[Invited Talk]
Non-contact High-Speed Data Links for Memory Interfaces
Hiroki Ishikuro, Won-Joo Yun, Shinya Nakano, Wataru Mizuhara, Atsutake Kosuge, Noriyuki Miura, Tadahiro Kuroda (Keio Univ.)
pp. 31 - 36
ICD2012-8
4-Times Faster Rising Vpass (10V), 15% Lower Power Vpgm (20V), Wide Output Voltage Range Voltage Generator System for 4-Times Faster 3D-integrated Solid-State Drives
Teruyoshi Hatanaka, Ken Takeuchi (Univ. of Tokyo)
pp. 37 - 42
ICD2012-9
Design of an MTJ-Based Fully Parallel Nonvolatile TCAM
Shoun Matsunaga, Takahiro Hanyu (Tohoku Univ.)
pp. 43 - 48
ICD2012-10
A Non-Volatile Content Addressable Memory Using Three-Terminal Magnetic Domain Wall Motion Cells
Ryusuke Nebashi, Noboru Sakimura, Yukihide Tsuji (NEC), Shunsuke Fukami (Tohoku Univ.), Hiroaki Honjo, Shinsaku Saito, Sadahiko Miura, Nobuyuki Ishiwata (NEC), Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno (Tohoku Univ.), Tadahiko Sugibayashi (NEC)
pp. 49 - 54
ICD2012-11
[Invited Talk]
Write-/Read- Disturb Issues and Circuit Solutions
Yuichiro Ishii, Yasumasa Tsukamoto, Koji Nii, Hidehiro Fujiwara, Makoto Yabuuchi, Koji Tanaka, Shinji Tanaka, Yasuhisa Shimazaki (Renesas Electronics)
pp. 55 - 60
ICD2012-12
[Invited Talk]
57% Faster Read, 31% Lower Read Energy, 256-Times Faster Injection 6T-SRAM with a Carrier-Injection Scheme to Pinpoint and Repair Disturb Fails
Kousuke Miyaji (Univ. of Tokyo), Toshikazu Suzuki (Panasonic), Shinji Miyano (STARC), Ken Takeuchi (Univ. of Tokyo)
pp. 61 - 66
ICD2012-13
0.4V SRAM with Bit Line Swing Suppression Charge Share Hierarchical Bit Line Scheme
Shinichi Moriwaki, Atsushi Kawasumi (STARC), Toshikazu Suzuki (Panasonic), Yasue Yamamoto, Shinji Miyano, Hirofumi Shinohara (STARC), Takayasu Sakurai (Univ. of Tokyo)
pp. 67 - 71
ICD2012-14
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme
Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura (Kobe Univ.), Toshikazu Suzuki, Shinji Miyano (STARC), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.)
pp. 73 - 78
ICD2012-15
Device-Conscious Circuit Designs for 0.5-V High-Speed Nanoscale CMOS LSIs
Akira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya (Hitachi), Masashi Horiguchi (Renesas)
pp. 79 - 84
ICD2012-16
Low-Energy Block-Level Instantaneous Comparison 7T SRAM for Dual Modular Redundancy
Yohei Umeki, Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ./JST)
pp. 85 - 90
ICD2012-17
A Chip-ID Generating Circuit for Dependable LSI using Random Address Errors on Embedded SRAM and On-Chip Memory BIST
Hidehiro Fujiwara, Makoto Yabuuchi, Hirofumi Nakano, Hiroyuki Kawai, Koji Nii, Kazutami Arimoto (Renesas Electronics)
pp. 91 - 95
ICD2012-18
A 128-bit Chip Identification Generating Scheme Exploiting SRAM Bitcells with Failure Rate of 4.45X 10-19
Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.), Masahiko Yoshimoto (Kobe Univ., JST CREST)
pp. 97 - 102
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.