IEICE Technical Report

Print edition: ISSN 0913-5685      Online edition: ISSN 2432-6380

Volume 113, Number 221

Reconfigurable Systems

Workshop Date : 2013-09-18 - 2013-09-19 / Issue Date : 2013-09-11

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Table of contents

RECONF2013-20
[Invited Talk] Study on Processor Architecture for Image Recognition
Masayuki Miyama (Kanazawa Univ.)
pp. 1 - 6

RECONF2013-21
An Implementation of High Performance Stream Processing on a Reconfigurable Hardware
Eric Shun Fukuda (Hokkaido Univ.), Hideyuki Kawashima (Univ. of Tsukuba), Hiroaki Inoue (NEC), Taro Fujii, Koichiro Furuta (Renesas Electronics), Tetsuya Asai, Masato Motomura (Hokkaido Univ.)
pp. 7 - 12

RECONF2013-22
Design and Evaluation of Stream Processor for Incompressive Fluid Computation based on Fractional-Step Method
Ryotaro Chiba, Hayato Suzuki, Ryo Ito, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.)
pp. 13 - 18

RECONF2013-23
A Power-Performance model for 3-D stencil computation on an FPGA accelerator
Keisuke Dohi, Kota Fukumoto, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)
pp. 19 - 24

RECONF2013-24
A Restricted Dynamically Reconfigurable Architecture for Low Power Processors
Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura (Hokkaido Univ.)
pp. 25 - 30

RECONF2013-25
Nonvolatile reconfigurable device development platform using a phase change material
Takumi Michida, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.), Kenichi Shimomai, Takashi Ishiguro (TAIYO YUDEN)
pp. 31 - 36

RECONF2013-26
A Low power Reconfigurable Accelerator using a Back-gate Bias Control Technique
Hongliang Su, Weihan Wang, Hideharu Amano (Keio Univ.)
pp. 37 - 42

RECONF2013-27
A LUT Architecture Based on Partial Function of Shannon Expansion
Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 43 - 48

RECONF2013-28
Investigation of the area reduction by pass transistor logic in reconfigurable device MPLD
Yuki Yoshida, Takumi Michida, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.), Kenichi Shimomai, Takashi Ishiguro (TAIYO YUDEN)
pp. 49 - 54

RECONF2013-29
Hardware Acceleration of Inverted Pendulum Control Processing by Using the High Level Synthesis Tool JavaRock
Daichi Uetake, Takeshi Ohkawa (Utsunomiya Univ.), Takefumi Miyoshi (e-trees), Takashi Yokota, Kanemitsu Ootsu (Utsunomiya Univ.)
pp. 55 - 60

RECONF2013-30
Design method for hw/sw Complex System
Yuichi Ogishima, Masatoshi Sekine (Tokyo Univ. of Agriculture and Tech.)
pp. 61 - 66

RECONF2013-31
A Low Power Oriented Design Framework for Considering Reconfiguration Time on Embedded Systems
Koichi Araki, Yukinori Sato, Yasushi Inoguchi (JAIST)
pp. 67 - 72

RECONF2013-32
The Circuit Configuration method of 3D FPGA-Array System "Vocalise"
Hiromasa Kubo, Jiang Li, Yusuke Atsumari, Baku Ogasawara, Masatoshi Sekine (Tokyo Univ. of Agliculture and Tech.)
pp. 73 - 78

RECONF2013-33
A study of pipeline execution on PEACH2
Takaaki Miyajima, Takuya Kuhara (Keio Univ.), Toshihiro Hanawa (Tsukuba Univ.), David Thomas (Imperial College), Hideharu Amano (Keio Univ.)
pp. 79 - 84

RECONF2013-34
A Packet Classifier using Parallel EVMDD(k) Machine
Hiroki Nakahara (Kagoshima Univ.), Tsutomu Sasao (Meiji Univ.), Munehiro Matsuura (Kyushu Inst. of Tech.)
pp. 85 - 90

RECONF2013-35
Development of Memory Management Framework for FPGA-based Prototyping
Shinya Takamaeda-Yamazaki (Tokyo Inst. of Tech./JSPS Research Fellow), Kenji Kise (Tokyo Inst. of Tech.)
pp. 91 - 96

RECONF2013-36
Considerations of Constantize for Entries in Associative Memories Using Dynamic Partial Reconfiguration
Tomoaki Ukezono, Koichi Araki (JAIST)
pp. 97 - 102

RECONF2013-37
Color configuration method for an optically reconfigurable gate array
Takumi Fujimori, Minoru Watanabe (Shizuoka Univ.)
pp. 103 - 108

RECONF2013-38
Optically reconfigurable gate array with a variable spot-size configuration context
Kouta Akagi, Minoru Watanabe (Shizuoka Univ.)
pp. 109 - 112

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan