Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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VLD2013-46
A Memory Based Filed Programmable Device for Energy saving MCUs
Tetsuya Matsumura (Nihon Univ.), Yoshifumi Kawamura (Renesas Electronics), Naoya Okada (Kanazawa Univ.), Kazutami Arimoto (Okayama Prefectual Univ.), Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.)
pp. 1 - 6
VLD2013-47
Proposal of Double-clock and Dual-Edge-Triggered Flip-flops for Asynchronous Circuits
Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII)
pp. 7 - 12
VLD2013-48
Construction of an Automatic Design Flow for Dual Pipelined Self-Synchronous Circuit
Atsushi Ito, Makoto Ikeda (Univ. of Tokyo)
pp. 13 - 18
VLD2013-49
[Invited Talk]
Technology Trends and Researches in Video Codec LSI
Satoshi Goto (Waseda Univ.)
p. 19
VLD2013-50
[Invited Talk]
Standardization of HEVC/H.265 and a Real-time Encoder
Hiroharu Sakate, Nobuaki Motoyama (Mitsubishi Electric)
p. 21
VLD2013-51
High Speed Block Motion Estimation (BME) Employing "Picture Frame shaped Search Window (PFSW)" for 8K Ultra High Definition Television (UHDTV)
Kentaro Seki, Tadayoshi Enomoto (Chuo Univ.)
pp. 23 - 28
VLD2013-52
A 2.4x-Real-Time VLSI Processor for 60-kWord Continuous Speech Recognition
Guangji He, Yuki Miyamoto, Kumpei Matsuda, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ)
pp. 29 - 34
VLD2013-53
Set Operating Processor (SOP)
-- Application for Image recognition --
Katsumi Inoue (AOT), Duc-Hung Le, Masahiro Sowa, Cong-Kha Pham (UEC)
pp. 35 - 40
VLD2013-54
A High-Level Synthesis Algorithm with Post-Silicon Delay Tuning for RDR Architectures and its Experimental Evaluations
Yuta Hagio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 41 - 46
VLD2013-55
Scan-based attack on the LED block cipher using scan signatures
Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 47 - 52
VLD2013-56
A Bi-Linear Interpolation Unit Using Selector Logics
Masashi Shio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 53 - 58
VLD2013-57
New Architecture for Multiple-Valued Fine-Grain Reconfigurable VLSI Based on Current-Mode Logic
Xu Bai, Michitaka Kameyama (Tohoku Univ.)
pp. 59 - 64
VLD2013-58
A Low Supply Voltage, Large "Read" Margin, Six-Transistor CMOS SRAM Employing Adaptively Lowering Word Line Voltage
Nobuaki Kobayashi, Tadayoshi Enomoto (Chuo Univ.)
pp. 65 - 70
VLD2013-59
A Delay-Locked Loop with Multi-Level Channel Length Decomposed Programming Delay Elements
Yu Zhang, Mingyu Li, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Bo Yang (Design Algorithm Lab)
pp. 71 - 76
VLD2013-60
A 9-bit, 20MS/s SAR ADC with A Design Strategy by Synthesizing Consideration of Layout-Dependent Effects
Gong Chen, Mingyu Li, Qing Dong, Shigetoshi Nakatake (Univ. of Kitakyushu), Bo Yang (Design Algorithm Lab)
pp. 77 - 82
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.