IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

Component Parts and Materials

Workshop Date : 2013-11-27 - 2013-11-28 / Issue Date : 2013-11-20

CPM2013-108
Automatic distortion compensation technique in resistor ladder for high-speed and low-power ADC
Wataru Yoshimura, Kenichi Ohhata (Kagoshima Univ.)
pp. 1 - 6

CPM2013-109
Co-design for reducing power supply noises with On-die PDN Impedance
Ryota Kobayashi, Hiroki Otsuka, Genki Kubo, Sho Kiyoshige, Wataru Ichimura, Masahiro Terasaki, Toshio Sudo (Shibaura Inst. of Tech.)
pp. 7 - 12

CPM2013-110
The design of Via Programmable Analog(VPA) circuit and its performance evaluation compared to programmable analog circuit
Keisuke Ueda, Ryohei Hori, Mitsuru Shiozaki, Toshio Kumamoto, Tomohiro Fujita, Takeshi Fujino (Ritsumeikan Univ.)
pp. 13 - 18

CPM2013-111
Performance Evaluation of Tamper-Resistant AES Cryptographic Circuit utilizing Hybrid Masking Dual-Rail ROM
Shintaro Ukai, Tsunato Nakai, Toshiki Kitamura, Takaya Kubota, Mitsuru Shiozaki, Takeshi Fujino (Ritsumeikan Univ.)
pp. 19 - 24

CPM2013-112
Design and study of PUF Circuit using IO-Masked Dual-Rail ROM with Resistance against Side-Channel Attacks
Takashi Nishimura, Syuuhei Sugaya, Akihiro Takeuchi, Mitsuru Shiozaki, Takeshi Fujino (Ritsumeikan Univ.)
pp. 25 - 30

CPM2013-113
A Quantizer Adaptively Predicting both Optimum Clock Frequency and Optimum Supply Voltage for Dynamic Voltage and Frequency Scaling Controlled Multimedia Processor
Nobuaki Kobayashi, Tadayoshi Enomoto (Chuo Univ.)
pp. 31 - 36

CPM2013-114
Low Energy Tracking System with Dynamic Frame-Rate Optimization
Serina Egawa, Koji Inoue (Kyushu Univ.)
pp. 37 - 42

CPM2013-115
Exploring Microarchitecture for Next Generation Single-Flux-Quantum Processors
Jumpei Yokota, Tomonori Tsuhata, Koji Inoue (Kyushu Univ.), Masamitsu Tanaka (Nagoya Univ.)
pp. 43 - 48

CPM2013-116
A Method for Optimizing Power-Efficiency of an MTJ-Based Nonvolatile FPGA
Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Takahiro Hanyu (Tohoku Univ.)
pp. 49 - 53

CPM2013-117
[Invited Talk] Circuit design for 3D-stacking using TSV interconnects
Kenichi Osada, Futoshi Furuta, Kenichi Takeda (Hitachi)
pp. 55 - 58

CPM2013-118
[Invited Talk] 3D Clock Distribution Using Vertically/Horizontally Coupled Resonators
Yasuhiro Take, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda (Keio Univ.)
pp. 59 - 62

CPM2013-119
[Invited Talk] Cu Wiring Technology for 3D/2.5D Packaging
Motoaki Tani, Yoshihiro Nakata, Tsuyoshi Kanki, Tomoji Nakamura (Fujitsu Lab.)
pp. 63 - 68

CPM2013-120
[Invited Talk] Chip Thinning Technologies for Chip Stacking Packages
Shinya Takyu, Tetsuya Kurosawa (Toshiba)
pp. 69 - 74

CPM2013-121
[Keynote Address] The age of Space Discovery Opened by World's First Solar Sail "IKAROS"
Osamu Mori (JAXA)
pp. 75 - 79

CPM2013-122
[Invited Talk] Toward VLSI Reliability Enhancement by Reconfigurable Architecture
Takao Onoye, Masanori Hashimoto (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Dawood Alnajjar, Hiroaki Konoura (Osaka Univ.)
p. 81

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan