IEICE Technical Report

Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380

VLSI Design Technologies

Workshop Date : 2016-05-11 / Issue Date : 2016-05-04

VLD2016-1
An Application of Subgradient Method to Delay Analysis
Hiroshi Miyashita, Koutaro Kawaraguchi (The Univ. of Kitakyushu)
pp. 1 - 4

VLD2016-2
Self-Aligned Double Patterning-Aware Two-color Grid Routing
Hatsuhiko Miura, Mitsuru Hasegawa, Taku Hirukawa, Kunihiro Fujiyoshi (TUAT)
pp. 5 - 10

VLD2016-3
Multi bit soft error tolerant FPGA architecture
Yuji Nakamura, Takuya Teraoka, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 35 - 40

VLD2016-4
A High-Level Synthesis Algorithm using Critical Path Optimization Based Operation Chainings for RDR Architectures
Kotaro Terada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 41 - 46

VLD2016-5
MERP-CNN: A Memory-Efficient Reconfigurable Processor for Convolutional Neural Networks Based on FPGA
Xushen Han, Dajiang Zhou, Shinji Kimura (Waseda Univ.)
pp. 47 - 52

VLD2016-6
[Invited Talk] Challenges of DA Technologies for the Future -- For the Establishment of Next Generation DA Technologies --
Michiaki Muraoka (Kochi Univ.)
p. 53

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan