Online edition: ISSN 2432-6380
[TOP] | [2017] | [2018] | [2019] | [2020] | [2021] | [2022] | [2023] | [Japanese] / [English]
CPSY2020-22
(See Japanese page.)
pp. 1 - 6
CPSY2020-23
(See Japanese page.)
pp. 7 - 12
CPSY2020-24
Study on Design and Evaluation of Stream Processing Hardware for Sound Simulation by FDTD method
Hiroki Tada (JAIST), Tomohiro Ueno, Atsushi Koshiba, Kentaro Sano (R-CCS), Ryuta Kawano, Yasushi Inoguchi (JAIST)
pp. 13 - 18
CPSY2020-25
An implementation and evaluation of Fast Fourier Transform on FPGA for High-performance Computing
Takaaki Miyajima, Tomohiro Ueno, Kentaro Sano (RIKEN)
pp. 19 - 24
CPSY2020-26
[Invited Talk]
System Architecture and Interconnect Development for the Supercomputer "K" and "Fugaku"
Yuichiro Ajima (Fujitsu)
pp. 25 - 30
CPSY2020-27
(See Japanese page.)
pp. 31 - 34
CPSY2020-28
(See Japanese page.)
pp. 35 - 39
CPSY2020-29
Throughput improvement of Responsive Link with High Speed Transceiver in FPGA
Masahiko Takahashi, Yamasaki Nobuyuki (Keio Univ.)
pp. 40 - 45
CPSY2020-30
Evaluations of FPGA-based Neural Networks using of ODE
Hirohisa Watanabe, Hiroki Matsutani (Keio Univ.)
pp. 46 - 51
CPSY2020-31
Efficient Attention Mechanism by Softmax Function with Trained Coefficient
Kaito Hirota (UT), O'uchi Shinichi (AIST), Fujita Masahiro (UT)
pp. 52 - 57
CPSY2020-32
A High-speed Convolutional Neural Network Accelerator for an Adaptive Resolution on an FPGA
Koki Sayama, Akira Jinguji, Naoto Soga, Hiroki Nakahara (Tokyo Tech)
pp. 58 - 62
CPSY2020-33
Implementation of Quantized Deep Neural Network on FPGA
Pan Hongyi (AIST/The Univ. of Tokyo), Ben Ahmed Akram, Ikegami Tsutomu (AIST), Tominaga Kazuki (The Univ. of Tokyo), Kudoh Tomohiro (AIST/The Univ. of Tokyo)
pp. 63 - 68
CPSY2020-34
Residual signed-digit number - residual binary number conversion algorithm
Yuki Saba, Yuuki Tanaka, Shugang Wei (Gunma Univ.)
pp. 69 - 74
CPSY2020-35
Comparison of ICA Algorithms in the Compressed Sensing EEG Measurement Framework Using OD-ICA
Wataru Okumura, Daisuke Kanemoto, Osamu Maida, Tetsuya Hirose (Osaka Univ)
pp. 75 - 79
CPSY2020-36
Low Power EEG Measurement Using Compressed Sensing Consideration of the Sampling Interval
Yuki Okabe, Daisuke Kanemoto (Osaka Univ.), Tomoya Mochizuki (Yamanashi Univ.), Osamu Maida, Tetsuya Hirose (Osaka Univ.)
pp. 80 - 84
CPSY2020-37
High speed architectures of decimal counters
Shuhei Yanagawa, Yuuki Tanaka, Shugang Wei (Gunma Univ.)
pp. 85 - 89
CPSY2020-38
Acceleration of Database Query Processing Using FPGA
Hirohiko Ozaku (UEC), Masato Yoshimi (TIS), Celimuge Wu, Tsutomu Yoshinaga (UEC)
pp. 90 - 95
CPSY2020-39
FPGA Accelerator Design for Real-Time Object Detection
Koichiro Ban, Masanori Furuta, Daisuke Kobayashi (Toshiba)
pp. 96 - 100
CPSY2020-40
FPGA Implementation of Semantic Segmentation on LWIR Images for Autonomous Robot
Yuichiro Niwa (ATLA), Taiki Fujii (eSOL)
pp. 101 - 106
CPSY2020-41
(See Japanese page.)
pp. 107 - 112
CPSY2020-42
Network Intrusion Detection System based on Hybrid FPGA/GPU Pattern Matching
Shunta Kikuchi (AIST/The Univ. of Tokyo), Tsutomu Ikegami, Akram ben Ahmed (AIST), Tomohiro Kudoh (The Univ. of Tokyo/AIST), Ryohei Kobayashi, Norihisa Fujita, Taisuke Boku (Univ. of Tsukuba)
pp. 113 - 118
CPSY2020-43
Hiroaki Suzuki (Keio Univ), Wataru Takahashi (NEC), Kazutoshi Wakabayashi (Tokyo Univ), Hideharu Amano (Keio Univ)
pp. 119 - 124
CPSY2020-44
SLM based FPGA-IP soft core
Yuya Nakazato, Hiroaki Koga (Kumamoto Univ.), Zhao Qian (KIT), Motoki Amagasaki, Morihiro Kuga, Masahiro Iida (Kumamoto Univ.)
pp. 125 - 130
CPSY2020-45
Automated architecture exploration on Scala-based hardware development environment
Ryota Yamashita, Daichi Teruya, Hironori Nakajo (TUAT)
pp. 131 - 136
CPSY2020-46
A new method for evaluating corruption metric and resilience of logic locking
Shusaku Minami, Yusuke Matsunaga (Kyushu Univ.)
pp. 137 - 142
CPSY2020-47
Mutation-Based Fuzzing Using Data Structure Captured via Data Generator
Noriyuki Namba, Nagisa Ishiura (Kwansei Gakuin Univ.)
pp. 143 - 147
CPSY2020-48
Detection of Vulnerability Inducing Code Optimization Based on Binary Code
Yuka Azuma, Nagisa Ishiura (Kwansei Gakuin Univ.)
pp. 148 - 153
CPSY2020-49
Performance Testing of VRP Optimization of C Compilers by Random Program Generation
Daiki Murakami, Nagisa Ishiura (Kwansei Gakuin Univ.)
pp. 154 - 159
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.