Online edition: ISSN 2432-6380
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RECONF2024-106
Consideration of Logic Gate Structure Using Vertical Nanowire Transistors
Genta Nakamura (Kyushu Univ), Katsuhiro Tomioka (Hokkaido Univ), Koji Inoue (Kyushu Univ)
pp. 1 - 6
RECONF2024-107
Event-Wise Accurate Single-Event Upset Discrimination with Active Learning and Adaptive Hyperparameter Tuning
Ryuichi Yasuda, Kazusa Takami, Yuibi Gomi (Kyoto Univ.), Kozo Takeuchi (JAXA), Masanori Hashimoto (Kyoto Univ.)
pp. 7 - 12
RECONF2024-108
Implementation of an Error Correcting Decoder for Surface Code Using Greedy Algorithm on ASIC by RTL and Behavioral Synthesis
Ren Aoyama (KIT), Junichiro Kaodomoto (UTokyo), Kazutoshi Kobayashi (KIT)
pp. 13 - 17
RECONF2024-109
(See Japanese page.)
pp. 18 - 22
RECONF2024-110
An FPGA Implementation of Object Tracking System using Center of Mass Computation with Integral Images
Yusuke Hara, Shinji Fukuma (Fukui Univ)
pp. 23 - 28
RECONF2024-111
Stabilization Techniques for Online Computation-Oriented Linear Equation Solvers Targeting FPGA Implementation
Yuma Omoto, Yuya Shuto, Atsushi Kubota, Tetsuo Hironaka (Hiroshima City Univ.)
pp. 29 - 34
RECONF2024-112
Global Routing for CBA-based 3D Flash Memory
Masayuki Shimoda, Atsushi Takahashi (Science Tokyo), Kosuke Yanagidaira, Mikiko Hirai (KIOXIA), Toshikazu Watanabe, Toshimitsu Iwasawa (KIOXIA Systems), Chikaaki Kodama (KIOXIA)
pp. 35 - 40
RECONF2024-113
(See Japanese page.)
pp. 41 - 46
RECONF2024-114
Efficient FPGA Implementation of Compressor Trees Based on Generalized Parallel Counter Chains
Mugi Noda, Nagisa Ishiura (Kwansei Gakuin Univ.)
pp. 47 - 52
RECONF2024-115
Hardware Design Using Python for Full Hardware Implementation of RTOS-Based Systems
Hikaru Shiga, Nagisa Ishiura (Kansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM)
pp. 53 - 58
RECONF2024-116
(See Japanese page.)
pp. 59 - 63
RECONF2024-117
(See Japanese page.)
pp. 64 - 68
RECONF2024-118
A design hackathon aimed at sparking interest in semiconductors with an AI application
Takao Goto, Mizuho Nitami, Hideharu Amano, Atsutake Kosuge, Yuki Mitarai, Jiawei Yu, Yuxuan PAN, Makoto Ikeda (The Univ. of Tokyo)
pp. 69 - 74
RECONF2024-119
"Shochiku-V": CPU of "LAXER-SoC" for industrial edge devices
Daiki Matsunaga, Shozo Takeoka (AXE)
pp. 75 - 81
RECONF2024-120
Comparison of FPGA and OpenLane Implementations of a Single Instruction Set Computer
Ochirsogt Ariya (Tsukuba Univ./AIST), Yohei Hori, Toshihiro Katashita, Masakazu Hioki (AIST), Kenji Kanazawa (Tsukuba Univ.)
pp. 82 - 86
RECONF2024-121
Investigation of patch-based neural networks for super-resolution hardware
Junya Kibushi, Cong-Kha Pham (UEC)
pp. 87 - 90
RECONF2024-122
Design of Convolutional Neural Network Hardware with Systolic Array
Shu Oguro, Cong-Kha Pham (UEC)
pp. 91 - 94
RECONF2024-123
CNN accelerator using Winograd algorithm
Kota Saito, Cong-Kha Pham (UEC)
pp. 95 - 98
RECONF2024-124
[Invited Talk]
Challenge to reproduce CPU processing by reading/writing flash memory
Masahiro Kusaka (KIOXIA)
pp. 99 - 103
RECONF2024-125
Introduction and Evaluation of a Programmable Buffer for Stencil Computation on RIKEN CGRA
Takumi Okada, Yasunori Osana, Masahiro Iida (Kumamoto Univ.), Boma Adhi, Kentaro Sano (R-CCS), Omar Ragheb, Jason Anderson (UofT)
pp. 104 - 109
RECONF2024-126
Emulation Environment for Reconfigurable Virtual Accelerator (ReVA) with QEMU
Kaoru Kayukawa, Shunya Kawai, Kazuki Yaguchi (TUAT), Yasunori Osana (Kumamoto Univ.), Takefumi Miyoshi (Wasalabo, LCC.), Hironori Nakajo (TUAT)
pp. 110 - 115
RECONF2024-127
Development of Self-Calibration Hardware Interface for a Peripheral on Super General Purpose SoC
Hibiki Shinozaki, Akira Yamawaki (KIT)
pp. 116 - 121
RECONF2024-128
Proposal and evaluation of Heterostructure Clusters Using PAE Cells for eFPGA IP
Tatsuya Sasaki, Ryo Iwasaki, Kensyu Seto, Masahiro Iida (Kumamoto Univ.)
pp. 122 - 127
RECONF2024-129
A Graph Neural Network based approach for FPGA routing
Kazuki Tokuishi, Masato Kiyama, Motoki Amagasaki, Kenshu Seto (Kumamoto Univ.)
pp. 128 - 133
RECONF2024-130
An FPGA Implementation Using Non-binary LDPC Code for Continuous-Variable Quantum Key Distribution
Kaijie Wei (Keio Univ.), Devanshu Garg (Blueqat Inc.), Ryutaro Nagai (SCSK Corp.), Takao Tomono (Keio Univ.), Hideharu Amano (U.Tokyo)
pp. 134 - 139
RECONF2024-131
Clock distribution method on FPGAs without any dedicated clock tree
Ayumu Ogura, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.)
pp. 140 - 144
RECONF2024-132
Radiation degradation of the configuration circuit on a dynamic optically reconfigurable gate array
Seiji Ohashi, Minoru Watanabe, Nobuya Watanabe (Okayama Univ.)
pp. 145 - 149
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.