IEICE Technical Report

Online edition: ISSN 2432-6380

Computer Systems

Workshop Date : 2024-06-10 - 2024-06-12 / Issue Date : 2024-06-03

CPSY2024-1
FPGA Implementation of a One-Instruction-Set Computer and Evaluation of Power Consumption
Ariya Ochirtsogt, Kenji Kanazawa (Tsukuba Univ.)
pp. 1 - 5

CPSY2024-2
Study of control flow decoupling for controller design exploration in CGRA
Hisako Ito, Takuya Kojima, Hideki Takase, Hiroshi Namkamura (Univ. of Tokyo)
pp. 6 - 11

CPSY2024-3
Rapid Inter-Thread Communication Using Message Passing Unit in RISC-V SMT Processor
Go Akamatsu, Shogo Takata, Tomoaki Tanaka, Hironori Nakajo (TUAT)
pp. 12 - 17

CPSY2024-4

Akinobu Tomori, Yasunori Osana (Kumamoto Univ.)
pp. 18 - 22

CPSY2024-5
A preliminary report on an FPGA-based prototype of a network switch supporting Asynchronous Traffic Shaping for Time Sensitive Networking
Akram Ben Ahmed, Takahiro Hirofuchi, Takaaki Fukai (AIST)
pp. 23 - 29

CPSY2024-6

Yasuhiko Nakashima (NAIST)
pp. 30 - 35

CPSY2024-7
A preliminary evaluation of CNNs' performance of meteor detection using training data by generative AI towards FPGA implementation
Zheng Yuping, Kenji Kanazawa (Univ. Tsukuba)
pp. 36 - 39

CPSY2024-8
Fault classification and prediction of AI accelerators based on activation maximization
Ma Shanmou, Kazuteru Namba (Chiba Univ.)
pp. 40 - 45

CPSY2024-9
A LBIST Method for Detecting Fault Locations in AI Accelerators
Zhang Jiaxi, Namba Kazuteru (Chiba Univ)
pp. 46 - 51

CPSY2024-10
Burst Length Optimization in MLC PCM using Encoding and Merge Sort
Jin Lei, Kazuteru Namba (Chiba Univ.)
pp. 52 - 57

CPSY2024-11
(See Japanese page.)
pp. 58 - 63

CPSY2024-12
A Framework for Efficient Evaluation of Side-Channel Attack Resistance -- A Case Study of HLS-designed AES --
Takuya Kojima (UTokyo)
pp. 64 - 69

CPSY2024-13
On the Design and Implementation of Point Cloud-Based Applications with Pynq and High-Level Synthesis
Keisuke Sugiura (Keio Univ.)
pp. 70 - 72

CPSY2024-14
Exploration and Simulation of FPGA Utilizing 3D-SRAM
Ryo Takahashi (Tokyo Tech), Hiroki Nakahara (Tohoku Univ.)
pp. 73 - 78

CPSY2024-15
Memory-centric CGRA with variable parallelism for neural networks
Atsushi Hori, Fumiya Arai, Tetsuya Asai, Kota Ando (Hokkaido Univ.)
pp. 79 - 84

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan