Online edition: ISSN 2432-6380
[TOP] | [2020] | [2021] | [2022] | [2023] | [2024] | [2025] | [2026] | [Japanese] / [English]
DC2026-1
Future Directions and Implementation of an Integrated Software Stack for Diverse AI Workloads on CGLA
Takuto Ando, Yoshifumi Munakata, Yasuhiko Nakashima (NAIST)
pp. 1 - 6
DC2026-2
Scalability Evaluation of CGLA \with High-Bandwidth Memory for LLM Inference
Yoshifumi Munakata, Takuto Ando, Yasuhiko Nakashima (NAIST)
pp. 7 - 10
DC2026-3
Reduction of Processing for FPGA-Parallelization of a Piano Simulator
Masatsugu Okazaki, Eiji Tominaga (YAMAHA)
pp. 11 - 16
DC2026-4
Minimizing Global Routing via Optimal Clustering for PAEs Using ILP
Soi Terada, Miyu Yoshida, Ryo Iwasaki, Masahiro Iida (Kumamoto Univ)
pp. 17 - 22
DC2026-5
Synchronization Primitive for EoP Signals and Data in Elastic CGRAs
Junsei Tabata (Kumamoto Univ.), Boma Adhi (RIKEN), Omkar Bhilare, Hamas Waqar (UofT), Omar Ragheb (Fujitsu Consulting (Canada) Inc.), Kentaro Sano (RIKEN), Jason Anderson (UofT), Tomohiro Ueno (RIKEN), Yasunori Osana (Kumamoto Univ.)
pp. 23 - 28
DC2026-6
A Study on Automatic Directive Insertion in HLS
Keisuke Takano (JAIST), Yasushi Inoguchi (Kanazawa Univ.)
pp. 29 - 32
DC2026-7
(See Japanese page.)
pp. 33 - 37
DC2026-8
A Don't Care Filling Algorithm to Improve Estimated Field Random Testability Using Multiple Functional Time Expansion Models
Kazuki Nakamoto, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ)
pp. 38 - 43
DC2026-9
A Control Point Insertion Method to Increase the Estimated Number of Distinguishable Fault Pairs at Register Transfer Level
Yeongkyeong Yun, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ), Koji Yamazaki (Meiji Univ), Masayuki Arai (Nihon Univ)
pp. 44 - 49
DC2026-10
(See Japanese page.)
pp. 50 - 55
DC2026-11
(See Japanese page.)
pp. 56 - 61
DC2026-12
(See Japanese page.)
pp. 62 - 67
DC2026-13
Shunki Matsuo, Masahiro Aoyagi, Ohkawa Takeshi (Kumamoto Univ.)
pp. 68 - 73
DC2026-14
(See Japanese page.)
pp. 74 - 79
DC2026-15
Computation Skipping in a Variable-Parallelism Reconfigurable Architecture Through Pattern Analysis of Pruned Convolutional Kernels
Yu Inoue, Atsushi Hori, Takao Marukame, Tetsuya Asai (Hokkaido Univ.), Alexandre Schmid (EPFL), Kota Ando (Hokkaido Univ.)
pp. 80 - 85
DC2026-16
(See Japanese page.)
pp. 86 - 91
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.