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Technical Committee on Dependable Computing (DC)  (Searched in: 2017)

Search Results: Keywords 'from:2018-02-20 to:2018-02-20'
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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Ascending)
 Results 1 - 12 of 12  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2018-02-20
09:30		 Tokyo Kikai-Shinko-Kaikan Bldg. Note on Weighted Fault Coverage for Two-Pattern Tests
Masayuki Arai (Nihon Univ.), Kazuhiko Iwasaki (Tokyo Metro. Univ.) DC2017-77		 hrinking feature size and higher integration on semiconductor device manufacturing technology bring a problem of the gap... [more] DC2017-77
pp.1-6
DC 2018-02-20
09:55		 Tokyo Kikai-Shinko-Kaikan Bldg. A Test Register Assignment Method for Operational Units to Reduce the Number of Test Patterns for Transition Faults Using Controller Augmentation
Yuki Takeuchi, Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2017-78		 It is required to reduce the number of test patterns to reduce test cost for VLSIs. Especially, design-for-testability m... [more] DC2017-78
pp.7-12
DC 2018-02-20
10:35		 Tokyo Kikai-Shinko-Kaikan Bldg. Reduction of Wire Length by Reordering Delay Elements in Boundary Scan Circuit with Embedded TDC
Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) DC2017-79		 TSV attracts attention as a new implementation method of interconnects between dies in 3DICs.
However, faulty TSVs may ... [more]		 DC2017-79
pp.13-18
DC 2018-02-20
11:00		 Tokyo Kikai-Shinko-Kaikan Bldg. Locating Hot Spots with Justification Techniques in a Layout Design
Yudai Kawano, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen (Kyutech) DC2017-80		 In general, power consumption during LSI testing is higher than functional operation. Excessive power consumption in at-... [more] DC2017-80
pp.19-24
DC 2018-02-20
11:40		 Tokyo Kikai-Shinko-Kaikan Bldg. A test generation method based on k-cycle testing for finite state machines
Yuya Kinoshita, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2017-81		 Recent advances in semiconductor technologies have resulted in VLSI circuit density and complexity. As a result, efficie... [more] DC2017-81
pp.25-30
DC 2018-02-20
12:05		 Tokyo Kikai-Shinko-Kaikan Bldg. On generating locating arrays using simulated annealing
Tatsuya Konishi, Hideharu Kojima, Hiroyuki Nakagawa, Tatsuhiro Tsuchiya (Osaka Univ.) DC2017-82		 Combinatorial interaction testing is an efficient software testing strategy. In this paper, we focus on locating arrays ... [more] DC2017-82
pp.31-35
DC 2018-02-20
14:00		 Tokyo Kikai-Shinko-Kaikan Bldg. A Note on Stateless Avoidance Routing in Ad Hoc Networks
Tomonori Maeda, Kazuya Sakai, Satoshi Fukumoto (Tokyo Metropolitan Univ.) DC2017-83		  [more] DC2017-83
pp.37-42
DC 2018-02-20
14:25		 Tokyo Kikai-Shinko-Kaikan Bldg. A Golden-Free Hardware Trojan Detection Technique Considering Intra-Die Variation
Fakir Sharif Hossain, Tomokazu Yoneda, Michihiro Shintani, Michiko Inoue (NAIST), Alex Orailoglu (Univ. of California, San Diego) DC2017-84		 High detection sensitivity in the presence of process variation is a key challenge for hardware Trojan detection through... [more] DC2017-84
pp.43-48
DC 2018-02-20
15:05		 Tokyo Kikai-Shinko-Kaikan Bldg. A method for improving an estimation accuracy of a specific temperature and voltage range in a digital temperature and voltage sensor
Kenji Inoue, Yousuke Miyake, Seiji Kajihara (Kyutech) DC2017-85		 An RO(Ring Oscillator)-based digital temperature and voltage sensor has been proposed in order to measure an on-chip tem... [more] DC2017-85
pp.49-54
DC 2018-02-20
15:30		 Tokyo Kikai-Shinko-Kaikan Bldg. Investigation of a Measurement Method of Characteristic Variations in the FPGA Considering an LUT Structure
Kouhei Satou, Yukiya Miura (Tokyo Metropolitan Univ.) DC2017-86		 FPGAs (Field Programmable Gate Arrays) are integrated circuits that can implement arbitrary logic functions by reconfigu... [more] DC2017-86
pp.55-60
DC 2018-02-20
16:10		 Tokyo Kikai-Shinko-Kaikan Bldg. Testing the Bridge Interconnect Fault for Memory based Reconfigurable Logic Device (MRLD)
Senling Wang, Tatsuya Ogawa, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Masayuki Sato, Mitsunori Katsu (TRL), Shoichi Sekiguchi (TAIYOYUDEN) DC2017-87		 MRLD is a promising alternative to FPGA with the benefits of low production cost, low power and small delay. In order to... [more] DC2017-87
pp.61-66
DC 2018-02-20
16:35		 Tokyo Kikai-Shinko-Kaikan Bldg. Influence on Flip-Flop Behaviors by Power Supply Noise and Proposal of their Countermeasures
Miyuki Inoue, Yukiya Miura (Tokyo Metropolitan Univ.) DC2017-88		 With the scaling down and low power operation of VLSI circuits, effects on circuit behavior by power supply noise such a... [more] DC2017-88
pp.67-72
 Results 1 - 12 of 12  /   
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