|
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| Chair |
|
Kazutoshi Wakabayashi (NEC) |
| Vice Chair |
|
Atsushi Takahashi (Tokyo Inst. of Tech.) |
| Secretary |
|
Ichiro Kohno (Renesas), Nozomu Togawa (Waseda Univ.) |
|
|
|
| Chair |
|
Toshinori Sueyoshi (Kumamoto Univ.) |
| Vice Chair |
|
Syuuichi Sakai (Univ. of Tokyo), Yoshio Miki (Hitachi) |
| Secretary |
|
Morihiro Kuga (Kumamoto Univ.), Akira Asato (Fujitsu Labs.) |
| Assistant |
|
Hidetsugu Irie (Univ. of Tokyo) |
|
|
|
| Chair |
|
Hideharu Amano (Keio Univ.) |
| Vice Chair |
|
Nobuki Kajihara (NEC), Akira Nagoya (Okayama Univ.) |
| Secretary |
|
Masahiro Iida (Kumamoto Univ.), Tomonori Izumi (Ritsumeikan Univ.) |
| Assistant |
|
Yohei Hori (AIST) |
|
| Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) |
[schedule] [select]
|
|
| Chair |
|
Shinji Kimura |
| Secretary |
|
Yutaka Tamiya, Tohru Ishihara, Takashi Aoki |
|
| Conference Date |
Thu, Jan 29, 2009 08:40 - 17:50
Fri, Jan 30, 2009 08:40 - 17:25 |
| Topics |
|
| Conference Place |
Hiyoshi Campus, Keio University |
| Address |
Hiyoshi 4-1-1, kohoku-ku, Yokohama, Kanagawa, 223-8521 Japan |
| Transportation Guide |
http://www.keio.ac.jp/english/about_keio/campus_info/hiyoshi2.html |
Contact
Person |
Prof. Hideharu Amano
045-560-1063 |
Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Thu, Jan 29 AM
08:40 - 09:55 |
| (1) |
08:40-09:05 |
Implementation of Dynamically Reconfigurable Processor MuCCRA-3 and Methods for Reconfiguration Overhead Reduction  VLD2008-91 CPSY2008-53 RECONF2008-55 |
Toru Sano, Hideharu Amano (Keio Univ) |
| (2) |
09:05-09:30 |
Evaluation of a Multicore Reconfigurable Architecture VLD2008-92 CPSY2008-54 RECONF2008-56 |
Vu Manh Tuan, Hiroki Matsutani, Naohiro Katsura, Hideharu Amano (Keio Univ.) |
| (3) |
09:30-09:55 |
Power Reduction of Dynamically Reconfigurable Processor using Dual-Vth Technologies VLD2008-93 CPSY2008-55 RECONF2008-57 |
Keiichiro Hirai, Toru Sano, Masaru Kato, Hideharu Amano (Keio Univ.) |
| |
09:55-10:05 |
Break ( 10 min. ) |
Thu, Jan 29 AM
10:05 - 11:20 |
| (4) |
10:05-10:30 |
Implementation and evaluation of arithmetic circuit for Poisson equation that aims at TFlops by using FPGA array VLD2008-94 CPSY2008-56 RECONF2008-58 |
Kazuki Sato, Baatarsuren Bars, Masatoshi Sekine (Tokyo Univ. of Agriculture and Tech.) |
| (5) |
10:30-10:55 |
FPGA Implementation of Metastability-based True Random Number Generator VLD2008-95 CPSY2008-57 RECONF2008-59 |
Hisashi Hata, Shuichi Ichikawa (TUT) |
| (6) |
10:55-11:20 |
A Proposal of Message Driven IP Core Interface VLD2008-96 CPSY2008-58 RECONF2008-60 |
Ryuta Sasaki, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) |
| |
11:20-12:20 |
Lunch ( 60 min. ) |
Thu, Jan 29 PM
12:20 - 13:35 |
| (7) |
12:20-12:45 |
A programmable 9-contexts optically reconfigurable gate arrays and its writer VLD2008-97 CPSY2008-59 RECONF2008-61 |
Shinya Kubota, Minoru Watanabe (Shizuoka Univ.) |
| (8) |
12:45-13:10 |
Perfect demonstration of a four-context Optically Reconfigurable Gate Array VLD2008-98 CPSY2008-60 RECONF2008-62 |
Takayuki Mabuchi, Minoru Watanabe (Shizuoka Univ.) |
| (9) |
13:10-13:35 |
Comparison evaluation of an inversion/non-inversion dynamic optically reconfiguration architecture VLD2008-99 CPSY2008-61 RECONF2008-63 |
Shinichi Kato, Minoru Watanabe (Shizuoka Univ.) |
| |
13:35-13:45 |
Break ( 10 min. ) |
Thu, Jan 29 PM
13:45 - 14:35 |
| (10) |
13:45-14:10 |
Circuit Partition Method with Time-multiplexed I/O VLD2008-100 CPSY2008-62 RECONF2008-64 |
Tatsuki Isomura (Univ. of Kitakyushu), Masato Inagi (Hiroshima City Univ.), Yasuhiro Takashima (Univ. of Kitakyushu), Yuichi Nakamura (NEC) |
| (11) |
14:10-14:35 |
An Efficient Cut Enumeration for Depth-Optimum Technology Mapping for LUT-based FPGAs |
Taiga Takata, Yusuke Matsunaga (Kyushu Univ.) |
| |
14:35-14:45 |
Break ( 10 min. ) |
Thu, Jan 29 PM
14:45 - 16:00 |
| (12) |
14:45-15:10 |
A Proposal of the Computer Architecture for Numbers of Arbitrary Word Length VLD2008-102 CPSY2008-64 RECONF2008-66 |
Shohei Hashimoto, Yuta Totsuka, Masamichi Makino, Hikaru Yasuda, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara (Tokyo Denki Univ.) |
| (13) |
15:10-15:35 |
Improvement of Execution Efficiency by Applying Unitable PE Architecture for MX Core VLD2008-103 CPSY2008-65 RECONF2008-67 |
Yuta Mizokami, Mitsutaka Nakano, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) |
| (14) |
15:35-16:00 |
An Experimental Linux Cluster System for Tests VLD2008-104 CPSY2008-66 RECONF2008-68 |
Koichi Kitano (Polytech.Univ.), Koji Teramoto (EHDO), Tadayoshi Horita (Polytech.Univ.) |
| |
16:00-16:10 |
Break ( 10 min. ) |
Thu, Jan 29 PM
16:10 - 17:50 |
| (15) |
16:10-16:35 |
Extension of High Level Synthesis system CCAP for AMP multi-core system desin VLD2008-105 CPSY2008-67 RECONF2008-69 |
Yoshiyuki Ishimori, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Nagoya Univ.), Hiroyuki Kanbara (ASTEM) |
| (16) |
16:35-17:00 |
A Tunable LSI Based on Timing Skew and Stall Adjustments VLD2008-106 CPSY2008-68 RECONF2008-70 |
Yayumi Uehara, Mineo Kaneko (JAIST) |
| (17) |
17:00-17:25 |
Fast Module Placement in Floorplan-aware High-level Synthesis VLD2008-107 CPSY2008-69 RECONF2008-71 |
Wataru Sato, Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
| (18) |
17:25-17:50 |
A Fast SIMD Processing Unit Synthesis Method with Optimal Pipeline Architecture for Application-specific Processors VLD2008-108 CPSY2008-70 RECONF2008-72 |
Takayuki Watanabe, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
Fri, Jan 30 AM
08:40 - 09:30 |
| (19) |
08:40-09:05 |
Automatic Equivalence Specification between Two Sequential Circuits in High-level Design VLD2008-109 CPSY2008-71 RECONF2008-73 |
Jinmei Xu, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita (University of Tokyo) |
| (20) |
09:05-09:30 |
Formal Verification Method for Protocol Transducer Using Automatically Generated Properties from Specification VLD2008-110 CPSY2008-72 RECONF2008-74 |
Fei Gao, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo) |
| |
09:30-09:40 |
Break ( 10 min. ) |
Fri, Jan 30 AM
09:40 - 11:20 |
| (21) |
09:40-10:05 |
Foreknown Regularity Arithmetic Processing Unit VLD2008-111 CPSY2008-73 RECONF2008-75 |
Jin Sato, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) |
| (22) |
10:05-10:30 |
Improvement of Search Efficiency by Principal Component Analysis for Analog Circuit Sizing of Operational Amplifier using Genetic Algorithm VLD2008-112 CPSY2008-74 RECONF2008-76 |
Yuji Takehara (Toyohashi Univ. Tech.), Masanori Natsui (Tohoku Univ.), Yoshiaki Tadokoro (Toyohashi Univ. Tech.) |
| (23) |
10:30-10:55 |
A study for accurate RTL timing modeling |
Shota Nakajima, Masahiro Fukui (Ritsumeikan Univ.) |
| (24) |
10:55-11:20 |
Interaction of Abstraction Processing for Creation of Ideas
-- An Electronic Brain like a thought of human being -- VLD2008-114 CPSY2008-76 RECONF2008-78 |
Tadayuki Hattori |
| |
11:20-12:20 |
Lunch ( 60 min. ) |
Fri, Jan 30 PM
Chair: Tohru Ishihara (Kyushu Univ.)
12:20 - 13:35 |
| (25) |
12:20-12:45 |
A Multi-layer Bus Architecture Optimization Algorithm for MPSoC in Embedded Systems VLD2008-115 CPSY2008-77 RECONF2008-79 |
Harunobu Yoshida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Masayoshi Tachibana (KUT) |
| (26) |
12:45-13:10 |
A Low Energy ASIP Synthesis Method Based on Reducing Instruction Memory Access VLD2008-116 CPSY2008-78 RECONF2008-80 |
Yuta Kobayashi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
| (27) |
13:10-13:35 |
Combine operation pattern extraction from CDFG for DSP generation VLD2008-117 CPSY2008-79 RECONF2008-81 |
Toshiyuki Kato, Takaaki Miyake, Shinichi Oomata, Hideto Nishikado, Hironori Yamauchi (Ritsumei Univ), Shiro Kobayashi (Asahi Kasei) |
| |
13:35-13:45 |
Break ( 10 min. ) |
Fri, Jan 30 PM
13:45 - 14:35 |
| (28) |
13:45-14:10 |
Customizing of Domain-Specific and Compact Reconfigurable HW VLD2008-118 CPSY2008-80 RECONF2008-82 |
Shogo Nakaya, Nobuki Kajihara, Toru Awashima (NEC) |
| (29) |
14:10-14:35 |
Delay Evaluation of 90nm CMOS Multi-Context FPGA for Large-Scale Circuit Emulation VLD2008-119 CPSY2008-81 RECONF2008-83 |
Naoto Miyamoto, Tadahiro Ohmi (Tohoku Univ.) |
| |
14:35-14:45 |
Break ( 10 min. ) |
Fri, Jan 30 PM
14:45 - 16:00 |
| (30) |
14:45-15:10 |
Implementation of Asynchronous Bus for GALS System VLD2008-120 CPSY2008-82 RECONF2008-84 |
Takehiro Hori, Tsugio Nakamura, Narito Fuyutsume, Hiroshi Kasahara, Teruo Tanaka (Tokyo Denki Univ.) |
| (31) |
15:10-15:35 |
A Study of Routing Architecture on Variable Grain Logic Cell for DSP Application VLD2008-121 CPSY2008-83 RECONF2008-85 |
Yoshiaki Satou, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) |
| (32) |
15:35-16:00 |
Research on an Interconnection Network of the Dynamically Reconfigurable Processor: MuCCRA VLD2008-122 CPSY2008-84 RECONF2008-86 |
Masaru Kato, Toru Sano, Hideharu Amano (Keio Univ) |
| |
16:00-16:10 |
Break ( 10 min. ) |
Fri, Jan 30 PM
16:10 - 17:25 |
| (33) |
16:10-16:35 |
An Architecture of Regular Expression Matching Machine for NIDS and Its FPGA Implementation VLD2008-123 CPSY2008-85 RECONF2008-87 |
Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ) |
| (34) |
16:35-17:00 |
An FPGA implementation of Gibbs sampling method towards high-speed motif search VLD2008-124 CPSY2008-86 RECONF2008-88 |
Yuka Sato, Junko Tazawa, Toshiaki Miyazaki (Univ. of Aizu) |
| (35) |
17:00-17:25 |
Fast Solution of Link Disjoint Path Algorithm on Parallel Reconfigurable Processor DAPDNA-2 VLD2008-125 CPSY2008-87 RECONF2008-89 |
Taku Kihara, Sho Shimizu, Shan Gao, Yutaka Arakawa, Naoaki Yamanaka (Keio Univ.), Akifumi Watanabe (IPFlex) |
| Contact Address and Latest Schedule Information |
| VLD |
Technical Committee on VLSI Design Technologies (VLD) [Latest Schedule]
|
| Contact Address |
Ichiro Kohno (Renesas Technology Corp.)
E- :  h  i      s
TEL: +81-42-312-5873 |
| Announcement |
See also VLD's homepage:
http://www.ieice.org/~vld/ |
| CPSY |
Technical Committee on Computer Systems (CPSY) [Latest Schedule]
|
| Contact Address |
Morihiro KUGA (Kumamoto Univ.)
TEL +81-96-342-3647, FAX +81-96-342-3599
E-:    am  -u |
| RECONF |
Technical Committee on Reconfigurable Systems (RECONF) [Latest Schedule]
|
| Contact Address |
Yohei HORI (AIST)
E-:   yaist
TEL: +81-29-861-5080 (Ext.)55459
FAX: +81-29-861-5909 |
| IPSJ-SLDM |
Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [Latest Schedule]
|
| Contact Address |
Tohru ISHIHARA (Associate Professor)
System LSI Research Center
Kyushu University
3-8-33, Momochihama, Sawara-ku,
Fukuoka-shi, 814-0001, JAPAN
Email: i   slrck shu-u
Phone: +81-92-847-5188
Fax: +81-92-847-5190 |
Last modified: 2009-01-16 18:27:44
|