|
|
| Chair |
|
Michiko Inoue (NAIST) |
| Vice Chair |
|
Satoshi Fukumoto (Tokyo Metropolitan Univ.) |
| Secretary |
|
Masayoshi Yoshimura (Kyoto Sangyo Univ.), Haruhiko Kaneko (Tokyo Inst. of Tech.) |
| Assistant |
|
Masayuki Arai (Nihon Univ.) |
|
| Conference Date |
Tue, Feb 20, 2018 09:30 - 17:00 |
| Topics |
VLSI Design and Test, etc. |
| Conference Place |
|
Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
| Registration Fee |
This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on DC. |
Tue, Feb 20 AM
09:30 - 10:20 |
| (1) |
09:30-09:55 |
Note on Weighted Fault Coverage for Two-Pattern Tests  DC2017-77 |
Masayuki Arai (Nihon Univ.), Kazuhiko Iwasaki (Tokyo Metro. Univ.) |
| (2) |
09:55-10:20 |
A Test Register Assignment Method for Operational Units to Reduce the Number of Test Patterns for Transition Faults Using Controller Augmentation DC2017-78 |
Yuki Takeuchi, Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) |
| |
10:20-10:35 |
Break ( 15 min. ) |
Tue, Feb 20 AM
10:35 - 11:25 |
| (3) |
10:35-11:00 |
Reduction of Wire Length by Reordering Delay Elements in Boundary Scan Circuit with Embedded TDC DC2017-79 |
Satoshi Hirai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) |
| (4) |
11:00-11:25 |
Locating Hot Spots with Justification Techniques in a Layout Design DC2017-80 |
Yudai Kawano, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen (Kyutech) |
| |
11:25-11:40 |
Break ( 15 min. ) |
Tue, Feb 20 AM
11:40 - 12:30 |
| (5) |
11:40-12:05 |
A test generation method based on k-cycle testing for finite state machines DC2017-81 |
Yuya Kinoshita, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) |
| (6) |
12:05-12:30 |
On generating locating arrays using simulated annealing DC2017-82 |
Tatsuya Konishi, Hideharu Kojima, Hiroyuki Nakagawa, Tatsuhiro Tsuchiya (Osaka Univ.) |
| |
12:30-14:00 |
Break ( 90 min. ) |
Tue, Feb 20 PM
14:00 - 14:50 |
| (7) |
14:00-14:25 |
A Note on Stateless Avoidance Routing in Ad Hoc Networks DC2017-83 |
Tomonori Maeda, Kazuya Sakai, Satoshi Fukumoto (Tokyo Metropolitan Univ.) |
| (8) |
14:25-14:50 |
A Golden-Free Hardware Trojan Detection Technique Considering Intra-Die Variation DC2017-84 |
Fakir Sharif Hossain, Tomokazu Yoneda, Michihiro Shintani, Michiko Inoue (NAIST), Alex Orailoglu (Univ. of California, San Diego) |
| |
14:50-15:05 |
Break ( 15 min. ) |
Tue, Feb 20 PM
15:05 - 15:55 |
| (9) |
15:05-15:30 |
A method for improving an estimation accuracy of a specific temperature and voltage range in a digital temperature and voltage sensor DC2017-85 |
Kenji Inoue, Yousuke Miyake, Seiji Kajihara (Kyutech) |
| (10) |
15:30-15:55 |
Investigation of a Measurement Method of Characteristic Variations in the FPGA Considering an LUT Structure DC2017-86 |
Kouhei Satou, Yukiya Miura (Tokyo Metropolitan Univ.) |
| |
15:55-16:10 |
Break ( 15 min. ) |
Tue, Feb 20 PM
16:10 - 17:00 |
| (11) |
16:10-16:35 |
Testing the Bridge Interconnect Fault for Memory based Reconfigurable Logic Device (MRLD) DC2017-87 |
Senling Wang, Tatsuya Ogawa, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Masayuki Sato, Mitsunori Katsu (TRL), Shoichi Sekiguchi (TAIYOYUDEN) |
| (12) |
16:35-17:00 |
Influence on Flip-Flop Behaviors by Power Supply Noise and Proposal of their Countermeasures DC2017-88 |
Miyuki Inoue, Yukiya Miura (Tokyo Metropolitan Univ.) |
| Announcement for Speakers |
| General Talk | Each speech will have 20 minutes for presentation and 5 minutes for discussion. |
| Contact Address and Latest Schedule Information |
| DC |
Technical Committee on Dependable Computing (DC) [Latest Schedule]
|
| Contact Address |
|
Last modified: 2017-12-25 16:43:41
|