|
|
| Chair |
|
Toshiyuki Shibuya (Fujitsu Labs.) |
| Vice Chair |
|
Yusuke Matsunaga (Kyushu Univ.) |
| Secretary |
|
Noriyuki Minegishi (Mitsubishi Electric), Hiroyuki Tomiyama (Ritsumeikan Univ.) |
| Assistant |
|
Takehiro Miyazawa (MMS), Ryo Yamamoto (Mitsubishi Electric) |
|
|
|
| Chair |
|
Tsutomu Yoshinaga (Univ. of Electro-Comm.) |
| Vice Chair |
|
Akira Asato (Fujitsu), Yasuhiko Nakajima (NAIST) |
| Secretary |
|
Koji Nakano (Hiroshima Univ.), Hidetsugu Irie (Univ. of Electro-Comm.) |
| Assistant |
|
Hiroaki Inoue (NEC), Takeshi Ohkawa (Utsunomiya Univ.) |
|
|
|
| Chair |
|
Tetsuo Hironaka (Hiroshima City Univ.) |
| Vice Chair |
|
Minoru Watanabe (Shizuoka Univ.), Masato Motomura (Hokkaido Univ.) |
| Secretary |
|
Yutaka Yamada (Toshiba), Yoshiki Yamaguchi (Univ. of Tsukuba) |
| Assistant |
|
Kazuya Tanikagawa (Hiroshima City Univ.), Takefumi Miyoshi (e-trees.Japan) |
|
| Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) |
[schedule] [select]
|
|
| Chair |
|
Masahiro Fukui (Ritsumeikan Univ.) |
| Secretary |
|
Kotaro Shimamura (Hitachi), Makoto Sugihara (Kyushu Univ.), Masao Yokoyama (Sharp) |
|
| Conference Date |
Thu, Jan 29, 2015 08:35 - 18:20
Fri, Jan 30, 2015 08:30 - 17:50 |
| Topics |
FPGA Applications, etc |
| Conference Place |
|
Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Thu, Jan 29 AM
08:35 - 10:15 |
(1)
CPSY |
08:35-08:55 |
Performance Acceleration of Document-Oriented Stores Using GPUs  VLD2014-113 CPSY2014-122 RECONF2014-46 |
Shin Morishima, Hiroki Matsutani (Keio Univ.) |
(2)
CPSY |
08:55-09:15 |
Accelerating NOSQLs using FPGA NIC and In-Kernel Key-Value Cache VLD2014-114 CPSY2014-123 RECONF2014-47 |
Korechika Tamura, Ami Hayashi, Yuta Tokusashi, Hiroki Matsutani (Keio Univ.) |
(3)
CPSY |
09:15-09:35 |
An Online Outlier Detector for FPGA NICs VLD2014-115 CPSY2014-124 RECONF2014-48 |
Ami Hayashi, Yuta Tokusashi, Hiroki Matsutani (Keio Univ.) |
(4)
CPSY |
09:35-09:55 |
Turbo Boost Router: An On-Chip Router Supporting Deterministic and Adaptive Routings VLD2014-116 CPSY2014-125 RECONF2014-49 |
Natsuki Homma, Go Matsumura (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Hiroki Matsutani (Keio Univ.) |
(5)
CPSY |
09:55-10:15 |
NoC Architecture with Priority-based Packet Overtaking and Resource Control VLD2014-117 CPSY2014-126 RECONF2014-50 |
Shuhei Otsuki, Keigo Mizotani, Masayoshi Takasu (Keio Univ.), Daiki Yamazaki (Sony), Nobuyuki Yamasaki (Keio Univ.) |
| |
10:15-10:35 |
Break ( 20 min. ) |
Thu, Jan 29 AM
10:25 - 11:25 |
(6)
RECONF |
10:25-10:45 |
Radiation tolerance of parallel configuration of optically reconfigurable gate arrays VLD2014-118 CPSY2014-127 RECONF2014-51 |
Hiroyuki Ito, Retsu Moriwaki, Minoru Watanabe (Shizuoka Univ.) |
(7)
RECONF |
10:45-11:05 |
Circuit Design and Valuation of Reconfigurable Logic Circuit. VLD2014-119 CPSY2014-128 RECONF2014-52 |
Junki Kato, Shigeyoshi Watanabe, Hiroshi Ninomiya, Manabu Kobayashi, Yasuyuki Miura (SIT) |
(8)
RECONF |
11:05-11:25 |
Exploring 3D FPGA Architectures to Minimize the Number of Inter-layer Connections VLD2014-120 CPSY2014-129 RECONF2014-53 |
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
| |
11:25-12:35 |
Lunch Break ( 70 min. ) |
Thu, Jan 29 PM
12:45 - 13:35 |
(9)
RECONF |
12:45-13:35 |
[Invited Talk]
Human Friendly Robot Based on Ontologies VLD2014-121 CPSY2014-130 RECONF2014-54 |
Takahira Yamaguchi (Keio Univ.) |
Thu, Jan 29 PM
13:50 - 14:50 |
| (10) |
13:50-14:10 |
|
| (11) |
14:10-14:30 |
|
| (12) |
14:30-14:50 |
|
| |
14:50-15:05 |
Break ( 15 min. ) |
Thu, Jan 29 PM
15:05 - 16:25 |
(13)
RECONF |
15:05-15:25 |
An AWF Digital Spectrometer for a Radio Telescope VLD2014-122 CPSY2014-131 RECONF2014-55 |
Hiroki Nakahara (Ehime Univ.), Hiroyuki Nakanishi (Kagoshima Univ.), Kazumasa Iwai (NAOJ) |
(14)
RECONF |
15:25-15:45 |
Small Bandwidth Compression Hardware Exploited Distribution of Length of Prediction Residual VLD2014-123 CPSY2014-132 RECONF2014-56 |
Tomohiro Ueno, Ryo Ito, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.) |
(15)
RECONF |
15:45-16:05 |
Inter-Cube Data-Exchanging for Custom Fluid Computing Machine Based on Building-Cube Method VLD2014-124 CPSY2014-133 RECONF2014-57 |
Tomoya Ueno, Tomohiro Ueno, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.) |
(16)
RECONF |
16:05-16:25 |
FPGA Implementation of a High Time Resolution Signal Generation Circuit for PWM VLD2014-125 CPSY2014-134 RECONF2014-58 |
Shun Kashiwagi, Daiki Mitsutake, Hironobu Taniguchi, Yuichiro Shibata, Kiyoshi Oguri, Hidenori Maruta, Fujio Kurokawa (Nagasaki Univ.) |
| |
16:25-16:40 |
Break ( 15 min. ) |
Thu, Jan 29 PM
16:40 - 18:20 |
(17)
VLD |
16:40-17:00 |
Study on Clock Tree Delay Analysis Mechanism VLD2014-126 CPSY2014-135 RECONF2014-59 |
Goro Suzuki, Ryutaro Takeda (Kitakyushu Univ.) |
(18)
VLD |
17:00-17:20 |
Temperature sensor applying Body Bias in Silicon-on-Thin-BOX VLD2014-127 CPSY2014-136 RECONF2014-60 |
Tsubasa Kosaka, Shohei Nakamura, Kimiyoshi Usami (S.I.T.) |
(19)
VLD |
17:20-17:40 |
A Dual-mode Scheduling Strategy for Task Graphs with Data Parallelism VLD2014-128 CPSY2014-137 RECONF2014-61 |
Yang Liu, Lin Meng, Ittetsu Taniguchi, Hiroyuki Tomiyama (Ritsumeikan Univ.) |
(20)
VLD |
17:40-18:00 |
Analyzing the Impacts of Simultaneous Supply and Threshold Voltage Tuning on Energy Dissipation in VLSI Circuits VLD2014-129 CPSY2014-138 RECONF2014-62 |
Toshihiro Takeshita, Shinichi Nishizawa, AKM Mahfuzul Islam, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ) |
(21)
VLD |
18:00-18:20 |
CF3: Test suite for arithmetic optimization of C compilers VLD2014-130 CPSY2014-139 RECONF2014-63 |
Yusuke Hibino, Nagisa Ishiura (KGU) |
Fri, Jan 30 AM
08:30 - 10:10 |
(22)
RECONF |
08:30-08:50 |
Discussion on power performance optimization for stream processing on an FPGA accelerator VLD2014-131 CPSY2014-140 RECONF2014-64 |
Kota Fukumoto, Koji Okina, Rie Soejima, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) |
(23)
RECONF |
08:50-09:10 |
A proposal of a stream image compression architecture using neural networks VLD2014-132 CPSY2014-141 RECONF2014-65 |
Kaoru Hamasaki, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) |
(24)
RECONF |
09:10-09:30 |
Intrusion Detection in High-Speed Networks with a Multi-Byte Transition NFA VLD2014-133 CPSY2014-142 RECONF2014-66 |
Shin'ichi Wakabayashi, Tomoaki Hashimoto, Ryohei Koishi, Hiroki Takaguchi, Shinobu Nagayama, Masato Inagi (Hiroshima City Univ.) |
(25)
RECONF |
09:30-09:50 |
Implementation and Evaluation of the Low-level Communication Mechanism on FLOPS-2D VLD2014-134 CPSY2014-143 RECONF2014-67 |
Katsuki Kyan, Makoto Arakaki, Yusuke Hirai, Hiroki Nakasone (Univ. of the Ryukyus), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.), Yasunori Osana (Univ. of the Ryukyus) |
(26)
RECONF |
09:50-10:10 |
A feasibility study on implementing numerical applications on FPGAs using Vivado HLS VLD2014-135 CPSY2014-144 RECONF2014-68 |
Hiroki Nakasone, Yasunori Osana, Yasunori Nagata (Univ of Ryukyu) |
| |
10:10-10:30 |
Break ( 20 min. ) |
Fri, Jan 30 AM
10:30 - 12:10 |
(27)
VLD |
10:30-10:50 |
Error detection using residue signed-digit number arithmetic for arithmetic circuits VLD2014-136 CPSY2014-145 RECONF2014-69 |
Yoshitomo Nema, Yuuki Tanaka, Kazuhiro Motegi, Shugang Wei (Gunma Univ) |
(28)
VLD |
10:50-11:10 |
A Hardware Trojan Detection Method based on Trojan net features VLD2014-137 CPSY2014-146 RECONF2014-70 |
Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
(29)
VLD |
11:10-11:30 |
The proposal of the convex area maze router on LSI design automation VLD2014-138 CPSY2014-147 RECONF2014-71 |
Yohei Horino, Jun Hirayama, Yukiko Ohishi, Toshiyuki Tsutsumi (Meiji Univ.) |
(30)
VLD |
11:30-11:50 |
Detecting Missed Arithmetic Optimization Opportunities Using Random Testing of C Compilers VLD2014-139 CPSY2014-148 RECONF2014-72 |
Atsushi Hashimoto, Nagisa Ishiura (Kwansei Gakuin Univ.) |
(31)
VLD |
11:50-12:10 |
An FPGA Implementation of Deep Convolutional Neural Network using Synchronous Shift Data Transfer VLD2014-140 CPSY2014-149 RECONF2014-73 |
Li Ning, Yoichi Tomioka, Hitoshi Kitazawa (TUAT) |
| |
12:10-13:20 |
Lunch Break ( 70 min. ) |
Fri, Jan 30 PM
13:20 - 14:40 |
(32)
CPSY |
13:20-13:40 |
Implementation of Sparse Matrix-Vector Multiplication on GPU and Its Application to the Conjugate Gradient Method VLD2014-141 CPSY2014-150 RECONF2014-74 |
Shotaro Asano, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) |
(33)
CPSY |
13:40-14:00 |
Relaxing constraint conditions in parallelizing compiler based on a polyhedral model VLD2014-142 CPSY2014-151 RECONF2014-75 |
Toma Ogata, Hidehiro Nakano, Arata Miyauchi (Tokyo City Univ.) |
(34)
CPSY |
14:00-14:20 |
Acceleration of Big Data Partitioning with Multiple FPGA boards VLD2014-143 CPSY2014-152 RECONF2014-76 |
Ryu Kudo, Saori Sudo, Yasin Oge (UEC), Yuta Terada (AVAL DATA), Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga (UEC) |
(35)
CPSY |
14:20-14:40 |
Reliability Management in 2-layered Supervisor Processor VLD2014-144 CPSY2014-153 RECONF2014-77 |
Daiki Yamamoto, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ) |
| |
14:40-14:55 |
Break ( 15 min. ) |
Fri, Jan 30 PM
14:55 - 16:15 |
(36)
RECONF |
14:55-15:15 |
Design and Implementation of Portable and High-speed FPGA Accelerator employing USB3.0 VLD2014-145 CPSY2014-154 RECONF2014-78 |
Takuma Usui, Ryohei Kobayashi, Kenji Kise (Tokyo Tech) |
(37)
RECONF |
15:15-15:35 |
MieruSys Project : Developing an Advanced Computer System with Multiple FPGAs VLD2014-146 CPSY2014-155 RECONF2014-79 |
Yuki Matsuda, Eri Ogawa, Tomohiro Misono (Tokyo Tech), Naoki Fujieda, Shuichi Ichikawa (TUT), Kenji Kise (Tokyo Tech) |
(38)
RECONF |
15:35-15:55 |
FPGA Vendor Independent Descriptions and Designs of Synchronous FIFOs VLD2014-147 CPSY2014-156 RECONF2014-80 |
Tomonori Izumi (Ritsumeikan Univ.) |
(39)
RECONF |
15:55-16:15 |
Obfuscated Hardware Implementation of PLC Instructions with Opaque Predicates VLD2014-148 CPSY2014-157 RECONF2014-81 |
Kazuki Uyama, Naoki Fujieda, Shuichi Ichikawa (Toyohashi Tech.) |
| |
16:15-16:30 |
Break ( 15 min. ) |
Fri, Jan 30 PM
16:30 - 17:50 |
(40)
CPSY |
16:30-16:50 |
A Low Latency Real-Time Execution on Dependable Responsive Multithreaded Processor VLD2014-149 CPSY2014-158 RECONF2014-82 |
Keigo Mizotani, Yusuke Hatori, Yusuke Kumura, Masayoshi Takasu, Hiroyuki Chishiro, Nobuyuki Yamasaki (Keio Univ.) |
(41)
CPSY |
16:50-17:10 |
A Latency-Aware Packet Scheduling on Responsive Link VLD2014-150 CPSY2014-159 RECONF2014-83 |
Kouhei Oosawa, Shuma Hagiwara, Yusuke Kumura, Keigo Mizotani, Masayoshi Takasu, Nobuyuki Yamasaki (Keio Univ.) |
(42)
CPSY |
17:10-17:30 |
Real-time contour extraction for moving objects directly operating MPEG encoded data VLD2014-151 CPSY2014-160 RECONF2014-84 |
Syosuke Maruyama, Hidehiro Nakano, Arata Miyauchi (Tokyo City Univ.) |
(43)
CPSY |
17:30-17:50 |
A Cache to Cache Communication Strategy for Wireless 3D Multi-Core Processors VLD2014-152 CPSY2014-161 RECONF2014-85 |
Masataka Matsumura (UEC), Masaaki Kondo (Univ. Tokyo), Hiroki Matsutani (Keio Univ.), Yasutaka Wada (Waseda Univ.), Hiroki Honda (UEC) |
| Announcement for Speakers |
| General Talk | Each speech will have 17 minutes for presentation and 3 minutes for discussion. |
Last modified: 2015-01-15 09:02:52
|