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Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Yoshiki Yamaguchi (Tsukuba Univ.)
Vice Chair Yasushi Inoguchi (JAIST), Tomonori Izumi (Ritsumeikan Univ.)
Secretary Yuuki Kobayashi (NEC), Yukinori Sato (Toyohashi Univ. of Tech.)
Assistant Yukitaka Takemura (INTEL), Yasunori Osana (Kumamoto Univ.)

Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Shigetoshi Nakatake (Univ. of Kitakyushu)
Vice Chair Yuichi Sakurai (Hitachi)
Secretary Yukihiro Sasagawa (Socionext), Masashi Imai (Hirosaki Univ.)
Assistant Takuma Nishimoto (Hitachi)

Conference Date Mon, Jan 29, 2024 10:30 - 20:00
Tue, Jan 30, 2024 10:30 - 15:25
Topics FPGA Applications, etc. 
Conference Place kawasaki-Shinsangyosozo-Center AIRBIC Meeting Room #1-4 
Address 7-7 Shinkawasaki, Saiwai-ku, Kawasaki-shi, Kanagawa 212-0032 Japan
Transportation Guide 10min from JR Shin-kawasaki station, 15min from JR Kashimada station
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on RECONF, VLD.

Mon, Jan 29 AM 
10:30 - 12:10
(1) 10:30-10:55 Random number generation on the Rocket core with a built-in LFSR VLD2023-80 RECONF2023-83 Takayoshi Shikano, Shuichi Ichikawa (Toyohashi Tech.)
(2) 10:55-11:20 Suppression of output bit width growth in AFE stochastic computing units VLD2023-81 RECONF2023-84 Daiki Seto, Naoki Fujieda (Aichi Inst. Tech.)
(3) 11:20-11:45 VLD2023-82 RECONF2023-85
(4) 11:45-12:10 VLD2023-83 RECONF2023-86
  12:10-13:30 Lunch Break ( 80 min. )
Mon, Jan 29 PM 
13:30 - 14:20
(5) 13:30-14:20 [Invited Talk]
Role of FPGAs in Quantum Network Architectures VLD2023-84 RECONF2023-87
Fumiaki Mizuno (Keio Univ.)
  14:20-14:40 Break ( 20 min. )
Mon, Jan 29 PM 
14:40 - 16:20
(6) 14:40-15:05 VLD2023-85 RECONF2023-88
(7) 15:05-15:30 A Study of Low Latency Feedback Operation Architecture for Superconducting Qubit VLD2023-86 RECONF2023-89 Takefumi Miyoshi (QuEL/e-trees), Keisuke Koike (e-trees), Kazuhisa Ogawa, Ryo Matsuda, Hidehisa Shiomi (Osaka Univ.), Shinichi Morisaka (Osaka Univ./QuEL), Yutaka Tabuchi (RIKEN), Makoto Negoro (Osaka Univ.)
(8) 15:30-15:55 FPGA implementation of Data (De)Compression for State Vector Quantum Simulator VLD2023-87 RECONF2023-90 Kaijie Wei, Hideharu Amano (Keio Univ.), Ryohei Niwase (Tsukuba Univ.), Takefumi Miyoshi (WasaLabo), Yoshiki Yamaguchi (Tsukuba Univ.)
(9) 15:55-16:20 VLD2023-88 RECONF2023-91
  16:20-16:35 Break ( 15 min. )
Mon, Jan 29 PM 
16:35 - 17:50
(10) 16:35-17:00 High-speed division circuits using BCD codes VLD2023-89 RECONF2023-92 Fumiya Kanai, Yuki Tanaka (Gunma Univ.)
(11) 17:00-17:25 Derivation of an Evaluation Chip Spec suitable for Tester and Data Analysis
-- Toward comparative evaluation of latch-based and flip-flop-based circuits --
VLD2023-90 RECONF2023-93
Tadaaki Tanimoto, Keizo Hiraga, Toshihiko Katou, Kazuhiro Bessho, Toshimasa Shimizu (Sony Semiconductor Solutions)
(12) 17:25-17:50 Comparison of latch-based circuit and flip-flop-based circuit in actual device VLD2023-91 RECONF2023-94 Kenji Takahashi, Tadaaki Tanimoto, Keizo Hiraga, Masayuki Hayashi, Takato Inoue, Kazuhiro Bessho, Toshimasa Shimizu (Sony Semiconductor Solutions)
  17:50-18:00 Break ( 10 min. )
Mon, Jan 29 PM 
18:00 - 20:00
Tue, Jan 30 AM 
10:30 - 11:20
(13) 10:30-10:55 Design space exploration for a CGRA architecture that efficiently handles the Systolic algorithm VLD2023-92 RECONF2023-95 Hajime Takishita (Keio Univ.), Takuya Kojima (UTokyo), Hideharu Amano (Keio Univ.)
(14) 10:55-11:20 A Prototype Design of an Embedded Real-Time GPU VLD2023-93 RECONF2023-96 Takafumi Tarui, Nobuyuki Yamasaki (Keio Univ.)
  11:20-11:30 Break ( 10 min. )
Tue, Jan 30 PM 
11:30 - 12:00
  12:00-13:20 Lunch Break ( 80 min. )
Tue, Jan 30 PM 
13:20 - 14:10
(15) 13:20-13:45 Reduction of Circuit Size by Optimizing Status Registers in Full Hardware RTOS-Based Systems VLD2023-94 RECONF2023-97 Kei Mikami, Nagisa Ishiura (Kansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM)
(16) 13:45-14:10 Implementation of External Memory Access for Binary Synthesis Using General-Purpose High-Level Synthesizer VLD2023-95 RECONF2023-98 Sho Kishimoto, Nagisa Ishiukra (Kwansei Gakuin Univ.)
  14:10-14:25 Break ( 15 min. )
Tue, Jan 30 PM 
14:25 - 15:25
(17) 14:25-14:50 Exploration of Acceleration of FPGA-based Linear Equation Solver using Approximate Division in Electronic Circuit Simulator VLD2023-96 RECONF2023-99 Naoki Kakine, Shuto Yuya, Tetsuo Hironaka, Atsushi Kubota (HCU)
(18) 14:50-15:15 FPGA-Accelerated Random Forest for Real-Time IoT Intrusion Detection VLD2023-97 RECONF2023-100 Qingyu Zeng, Yuko Hara (Tokyo Tech)
(19) 15:15-15:25 Comparison of Graph Data Structures for Breadth-First Search Accelerator HyGTA2 VLD2023-98 RECONF2023-101 Jun Akimoto, Kazuya Tanigawa (Hiroshima City Univ), Kentaro Sano (Processor Research Team,RIKEN Center for Computational Science), Tetsuo Hironaka (Hiroshima City Univ)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address Chair: Yoshiki Yamaguchi (Tsukuba Univ.) 
Announcement RECONF website
RECONF slack
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Masashi IMAI (Hirosaki Univ. )
E--mail: bi-u 
Announcement See also VLD's homepage:

Last modified: 2024-01-29 09:34:09

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