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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
SDM |
2011-11-11 13:50 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Investigation of Scaling Limit Due to Short Channel Effects and Channel Boosting Leakage in Bulk and SOI NAND Flash Memory Cells Kousuke Miyaji, Chinglin Hung, Ken Takeuchi (Univ. of Tokyo) SDM2011-125 |
[more] |
SDM2011-125 pp.57-61 |
ICD |
2011-04-19 11:45 |
Hyogo |
Kobe University Takigawa Memorial Hall |
Suppress of Half Select Disturb in 8T-SRAM by Local Injected Electron Asymmetric Pass Gate Transistor Kousuke Miyaji, Kentaro Honda, Shuhei Tanakamaru (Univ. of Tokyo), Shinji Miyano (STARC), Ken Takeuchi (Univ. of Tokyo) ICD2011-13 |
8T-SRAM cell with asymmetric pass gate transistor by local electron injection is proposed to solve half select disturb. ... [more] |
ICD2011-13 pp.71-76 |
ICD |
2010-12-16 09:30 |
Tokyo |
RCAST, Univ. of Tokyo |
Elimination of Half Select Disturb in 8T-SRAM by Local Injected Electron Asymmetric Pass Gate Transistor Kentaro Honda, Kousuke Miyaji, Shuhei Tanakamaru (Univ. of Tokyo), Shinji Miyano (STARC), Ken Takeuchi (Univ. of Tokyo) ICD2010-95 |
8T-SRAM cell with asymmetric pass gate transistor by local electron injection is proposed to solve half select disturb. ... [more] |
ICD2010-95 pp.1-6 |
ICD, SDM |
2010-08-27 09:25 |
Hokkaido |
Sapporo Center for Gender Equality |
A 1.0V Power Supply, 9.5GByte/sec Write Speed, Single-Cell Self-Boost Program Scheme for Ferroelectric NAND Flash SSD Kousuke Miyaji, Shinji Noda, Teruyoshi Hatanaka (Univ. of Tokyo), Mitsue Takahashi, Shigeki Sakai (AIST), Ken Takeuchi (Univ. of Tokyo) SDM2010-139 ICD2010-54 |
A Single-Cell Self-Boost (SCSB) program scheme is proposed to achieve a 1.0V power supply operation in Ferroelectric (Fe... [more] |
SDM2010-139 ICD2010-54 pp.83-88 |
ICD, SDM |
2010-08-27 13:45 |
Hokkaido |
Sapporo Center for Gender Equality |
70% Read Margin Enhancement by VTH Mismatch Self-Repair in 6T-SRAM with Asymmetric Pass Gate Transistor by Zero Additional Cost, Post-Process, Local Electron Injection Kousuke Miyaji, Shuhei Tanakamaru, Kentaro Honda (Univ. of Tokyo), Shinji Miyano (STARC), Ken Takeuchi (Univ. of Tokyo) SDM2010-145 ICD2010-60 |
A VTH mismatch self-repair scheme in 6T-SRAM with asymmetric PG transistor by post-process local electron injection is p... [more] |
SDM2010-145 ICD2010-60 pp.115-120 |
SDM |
2010-06-22 15:15 |
Tokyo |
An401・402 Inst. Indus. Sci., The Univ. of Tokyo |
70% Read Margin Enhancement by VTH Mismatch Self-Repair in 6T-SRAM with Asymmetric Pass Gate Transistor by Zero Additional Cost, Post-Process, Local Electron Injection Kousuke Miyaji, Shuhei Tanakamaru, Kentaro Honda (Univ. of Tokyo), Shinji Miyano (STARC), Ken Takeuchi (Univ. of Tokyo) SDM2010-44 |
A VTH mismatch self-repair scheme in 6T-SRAM with asymmetric PG transistor by post-process local electron injection is p... [more] |
SDM2010-44 pp.61-65 |
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