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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM 2022-01-31
16:00		 Online Online [Invited Talk] ****
Keiichi Nakazawa, Junpei Yamamoto, Shigetaka Mori, Shintaro Okamoto, Akito Shimizu, Koichi Baba, Nobutoshi Fujii, Mutsuo Uehara, Katsunori Hiramatsu, Hideomi Kumano, Akira Matsumoto, Koichiro Zaitsu, Hidetoshi Ohnuma, Keiji Tatani, Tomoyuki Hirano, Hayato Iwamoto (Sony Semiconductor Solutions) SDM2021-73		 We developed a new structure of pixel transistors stacked over photodiode named “2-Layer Transistor Pixel Stacked CMOS I... [more] SDM2021-73
pp.20-23
CPM, LQE, ED 2016-12-13
11:20		 Kyoto Kyoto University Development of wafer structure and monolithic integrated GaN-μLED driver circuit for large-scale optoelectonic chip
Kazuaki Tsuchiyama, Shu Utsuhomiya, Shota Nakagawa, Keisuke Yamane, Hiroto Sekiguchi, Hiroshi Okada, Akihiro Wakahara (Toyohashi Tech.) ED2016-73 CPM2016-106 LQE2016-89		 A Si/SiO2/GaN-LED structure was fabricated by surface activated bonding method, and a GaN-µLED driver circuit consi... [more] ED2016-73 CPM2016-106 LQE2016-89
pp.79-83
SDM 2015-03-02
10:35		 Tokyo Kikai-Shinko-Kaikan Bldg [Invited Talk] Integration Technology of 3D FPGA with Performance Scalability and Function Flexibility
Kenichi Takeda, Mayu Aoki (Hitachi) SDM2014-163		 Three-layer stacked wafer with CMOS devices was demonstrated by using hybrid wafer bonding and via-last through silicon ... [more] SDM2014-163
pp.7-11
SDM 2014-01-29
15:30		 Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] 3D Integrated CMOS Device by Using Wafer Stacking and Via-last TSV
Mayu Aoki, Futoshi Furuta, Kazuyuki Hozawa, Yuko Hanaoka, Kenichi Takeda (Hitachi) SDM2013-145		 A three-layer-stacked wafer with CMOS devices was fabricated for the first time by using hybrid wafer bonding and backsi... [more] SDM2013-145
pp.43-46
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