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Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM 2011-10-21
14:00		 Miyagi Tohoku Univ. (Niche) [Invited Talk] Design Framework for Parameter Fluctuation in MOSFET Damaged by Ion Bombardment during Plasma Etching
Koji Eriguchi, Yoshinori Nakakubo, Asahiko Matsuda, Yoshinori Takao, Kouichi Ono (Kyoto Univ.) SDM2011-110		 We investigated the effects of plasma process-induced physical damage (bombardment of ions) on MOSFET performance degrad... [more] SDM2011-110
pp.73-78
VLD, ICD 2008-03-06
16:35		 Okinawa TiRuRu Comparison of Power consumption between dynamic voltage scheme and multi-supply voltage scheme for system LSI
Satoshi Hanami, Shigeyoshi Watanabe (Shonan Inst. of Tech.) VLD2007-155 ICD2007-178		 Reduction of power dissipation caused by dynamic current, gate leakage current, and subthreshold leakage current of mult... [more] VLD2007-155 ICD2007-178
pp.67-72
ICD, SIP, IE, IPSJ-SLDM 2006-10-27
10:50		 Miyagi   Design method of low-power dual-supply-voltage system LSI taking into account leakage current of MOSFET
Shigeyoshi Watanabe, Masaki Kanai, Akira Nagasawa, Satoshi Hanami, Manabu Kobayashi, Toshinori Takabatake (SIT) 		Reduction of power dissipation caused by dynamic current, gate leakage current, and subthreshold leakage current of dual... [more] SIP2006-106 ICD2006-132 IE2006-84
pp.31-36
ICD, VLD 2006-03-10
09:15		 Okinawa   Low Power Design of System LSI in the Presence of Leakage Current of MOSFET
Shigeyoshi Watanabe (Shonan Inst. of Tech.) 		Low power design of system LSI in the presence of leakage current has been described. By using parallel processing archi... [more] VLD2005-122 ICD2005-239
pp.1-6
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