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Technical Committee on VLSI Design Technologies (VLD) (Searched in: 2013)
Search Results: Keywords 'from:2013-05-16 to:2013-05-16'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, IPSJ-SLDM | 2013-05-16 09:00 |
Fukuoka | Kitakyushu International Conference Center | Performance-driven SRAM Macro Design with Parameterized Cell Considering Layout-dependent Effects Yu Zhang, Shigetoshi Nakatake (Univ. of Kitakyushu)  VLD2013-1 |
In nano-scale process, shallow trench isolation (STI) stress and well proximity effect (WPE) affect the threshold volta... [more] |
VLD2013-1 pp.1-6 |
| VLD, IPSJ-SLDM | 2013-05-16 09:25 |
Fukuoka | Kitakyushu International Conference Center | A Floorplan Method by Simulated Annealing and Sequence-pair for Asynchronous Circuits with Bundled-data Implementation Minoru Iizuka, Hiroshi Saito (Univ. of Aizu) VLD2013-2 |
[more] | VLD2013-2 pp.7-12 |
| VLD, IPSJ-SLDM | 2013-05-16 09:50 |
Fukuoka | Kitakyushu International Conference Center | A Longest Path Algorithm for Differential Pair Net Considering Connectivity Koji Yamazaki, Yukihide Kohira (Univ. of Aizu) VLD2013-3 |
In recent years, due to the speedup and miniaturization in LSI systems, PCB routing design uses many differential pair n... [more] | VLD2013-3 pp.13-18 |
| VLD, IPSJ-SLDM | 2013-05-16 13:00 |
Fukuoka | Kitakyushu International Conference Center | [Invited Talk]
A Note on Routing and Placement Yoji Kajitani (JAIST) VLD2013-4 |
[more] | VLD2013-4 pp.37-41 |
| VLD, IPSJ-SLDM | 2013-05-16 14:10 |
Fukuoka | Kitakyushu International Conference Center | Level Converter Design for Ultra Low Voltage Operation in Silicon-on-Thin-BOX MOSFET Shohei Nakamura, Kimiyoshi Usami (Shibaura Inst. of Tech.) VLD2013-5 |
Silicon on Thin Buried Oxide (SOTB) technology has an advantage that variation in threshold voltage can be more suppress... [more] | VLD2013-5 pp.43-48 |
| VLD, IPSJ-SLDM | 2013-05-16 14:35 |
Fukuoka | Kitakyushu International Conference Center | A Linear Interpolation Unit Using Selector Logics Masashi Shio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-6 |
Interpolation is a technique that presumes a value between existing data, which is often used for image scaling and cor... [more] |
VLD2013-6 pp.49-54 |
| VLD, IPSJ-SLDM | 2013-05-16 15:00 |
Fukuoka | Kitakyushu International Conference Center | Data Dependence Relaxation Techniques for Reducing Iteration Intervals in Pipelined Loops Shingo Kusakabe, Kenshu Seto (Tokyo City Univ.) VLD2013-7 |
In the loop pipelining of high-level synthesis, the sum of the delays in the cycles of the data dependence graph is a ma... [more] | VLD2013-7 pp.55-60 |
| VLD, IPSJ-SLDM | 2013-05-16 15:35 |
Fukuoka | Kitakyushu International Conference Center | Scan-based Attack against Trivium Stream Cipher Using Scan Signatures Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-8 |
Trivium is a synchronous stream cipher using three shift registers. It is designed to have a simple structure and runs a... [more] | VLD2013-8 pp.61-66 |
| VLD, IPSJ-SLDM | 2013-05-16 16:00 |
Fukuoka | Kitakyushu International Conference Center | A Zero Time and Area Overhead Fault-Secure High-Level Synthesis Algorithm for RDR Architectures Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2013-9 |
In this paper, we propose a zero time and area overhead fault-secure high-level synthesis algorithm for RDR architecture... [more] | VLD2013-9 pp.67-72 |
| VLD, IPSJ-SLDM | 2013-05-16 16:25 |
Fukuoka | Kitakyushu International Conference Center | SoC System Design Methodology with Fully-Coherent Cache Kodai Moritaka (NAIST), Hiroaki Yoshida, Mitsuru Tomono (FLA), Yasuhiko Nakashima (NAIST) VLD2013-10 |
As Chip Multi-Processors (CMPs) includes more processor cores in a single chip, the impact of its memory model on the en... [more] | VLD2013-10 pp.73-78 |
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