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Technical Committee on VLSI Design Technologies (VLD) (Searched in: 2015)
Search Results: Keywords 'from:2016-02-29 to:2016-02-29'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD | 2016-02-29 13:30 |
Okinawa | Okinawa Seinen Kaikan | Tool Support for Verifying Large Scale Hardware Design with Verilog-HDL Yuta Morimitsu, Tomoyuki Yokogawa (Okayama Prefectural Univ.), Masafumi Kondo, Hisashi Miyazaki (Kawasaki Univ. of Medical Welfare), Yoichiro Sato, Kazutami Arimoto (Okayama Prefectural Univ.), Norihiro Yoshida (Nagoya Univ.)  VLD2015-111 |
In this paper, we developed a tool supporting formal verification of large scale hardware design described by Verilog-HD... [more] | VLD2015-111 pp.1-6 |
| VLD | 2016-02-29 13:55 |
Okinawa | Okinawa Seinen Kaikan | Random Testing of C Compilers Based on Test Program Generation by Equivalence Transformation Kazuhiro Nakamura, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2015-112 |
This article proposes a method of generating test programs for random testing of C compilers based on equivalence transf... [more] | VLD2015-112 pp.7-12 |
| VLD | 2016-02-29 14:20 |
Okinawa | Okinawa Seinen Kaikan | Task Allocation Methods based on the Maximum Task Parallelism for Multi-core Systems with the DTTR Scheme Hiroshi Saito (Univ. Aizu), Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII) VLD2015-113 |
In this paper, we propose a task allocation method for multi-core systems with the Duplication with Temporary Triple Mo... [more] |
VLD2015-113 pp.13-18 |
| VLD | 2016-02-29 15:00 |
Okinawa | Okinawa Seinen Kaikan | High-Level Synthesis of Embedded Systems Controller from Erlang Hinata Takabeyashi, Nagisa Ishiura, Kagumi Azuma (Kwansei Gakuin Univ), Nobuaki Yoshida, Hiroyuki Kanbara (ASTEM) VLD2015-114 |
This article presents a method of specifying the behavior of embedded systems' control by a subset of Erlang and synthes... [more] | VLD2015-114 pp.19-24 |
| VLD | 2016-02-29 15:25 |
Okinawa | Okinawa Seinen Kaikan | A Multi-Paradigm High-Level Hardware Design Environment Shinya Takamaeda (NAIST) VLD2015-115 |
(To be available after the conference date) [more] | VLD2015-115 pp.25-30 |
| VLD | 2016-02-29 15:50 |
Okinawa | Okinawa Seinen Kaikan | ILP Based Synthesis of Soft-Error Tolerant Datapaths Considering Adjacency Constraint between Components Junghoon Oh, Mineo Kaneko (JAIST) VLD2015-116 |
As the device size decreases, the reliability degradation due to soft-errors is becoming one of the serious issues in VL... [more] | VLD2015-116 pp.31-36 |
| VLD | 2016-02-29 16:15 |
Okinawa | Okinawa Seinen Kaikan | A Note on the Optimization for Multi-Domain Latch-Based High-Level Synthesis Keisuke Inoue (KTC), Mineo Kaneko (JAIST) VLD2015-117 |
This paper discusses a high-level synthesis of new latch-based architecture, HLS-gls. The disadvantage of the conventio... [more] |
VLD2015-117 pp.37-42 |
| VLD | 2016-03-01 09:00 |
Okinawa | Okinawa Seinen Kaikan | A Packet Lookup Engine LSI Based on Mismatch Detection and Hash Search Yoshifumi Kawamura, Kousuke Imamura (Kanazawa Univ.), Naoki Miura, Masami Urano, Satoshi Shigematsu (NTT), Tetsuya Matsumura (Nihon Univ.), Yoshio Matsuda (Kanazawa Univ.) VLD2015-118 |
Developing an extremely efficient packet inspection algorithm for lookup engines is important to realize a high throughp... [more] | VLD2015-118 pp.43-48 |
| VLD | 2016-03-01 09:25 |
Okinawa | Okinawa Seinen Kaikan | A Screening Circuit for Intrusion Detection of High-Speed Networks and its FPGA Implementation Hiroki Takaguchi, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi (Hiroshima City Univ.) VLD2015-119 |
[more] | VLD2015-119 pp.49-54 |
| VLD | 2016-03-01 09:50 |
Okinawa | Okinawa Seinen Kaikan | Evaluation of Rotator-based Multiplexer Network with Control Circuits for Field-data Extractors Koki Ito, Kazushi Kawamura (Waseda Univ.), Yutaka Tamiya (Fujitsu Lab.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-120 |
In this paper, we evaluate the number of gates required for rotator-based MUX network including control circuits. Experi... [more] | VLD2015-120 pp.55-60 |
| VLD | 2016-03-01 10:30 |
Okinawa | Okinawa Seinen Kaikan | Electromagnetic Analysis Attack for Simeck and Simon Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) VLD2015-121 |
The risk of attack against IoT devices has been increased. Since IoT devices require constraint of area and power consum... [more] | VLD2015-121 pp.61-66 |
| VLD | 2016-03-01 10:55 |
Okinawa | Okinawa Seinen Kaikan | Power Analysis Attack for Countermeasure with Check Circuit Yoshiya Ikezaki, Masaya Yoshikawa (Meijo Univ.) VLD2015-122 |
The thread of side-channel attack against cryptgraphic circuit is pointed out. Side-channel attack is classified into tw... [more] | VLD2015-122 pp.67-72 |
| VLD | 2016-03-01 11:20 |
Okinawa | Okinawa Seinen Kaikan | Timing-error-tolerant AES Cipher Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-123 |
With the technologies advance, the importance of crypto circuits is increasing as well. AES cipher is well known as theo... [more] | VLD2015-123 pp.73-78 |
| VLD | 2016-03-01 11:45 |
Okinawa | Okinawa Seinen Kaikan | In-situ Hardware-Trojan Authentication for Invalidating Malicious Functions Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-124 |
[more] | VLD2015-124 pp.79-84 |
| VLD | 2016-03-01 13:30 |
Okinawa | Okinawa Seinen Kaikan | [Invited Talk]
VLSI Technology for Embedded Systems in the More than Moore Era
-- Focusing on Leading Edge Medical Applications -- Masaharu Imai, Yoshinori Takeuchi (Osaka Univ.) VLD2015-125 |
[more] | VLD2015-125 p.85 |
| VLD | 2016-03-01 14:45 |
Okinawa | Okinawa Seinen Kaikan | IP Design using High-Level Synthesis Design Flow Masato Tatsuoka, Ken Imanishi, Hidenori Nakaishi, Takeshi Toyoyama (SNI) VLD2015-126 |
In this paper we will describe practical experiences about the use of high level synthesis technologies to achieve highe... [more] | VLD2015-126 pp.87-92 |
| VLD | 2016-03-01 15:10 |
Okinawa | Okinawa Seinen Kaikan | FPGA Implementation of a Distributed-register Architecture Circuit Using floorplan-aware High-level Synthesis Koichi Fujiwara, Kawamura Kazushi, Keita Igarashi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-127 |
Recently, high-level synthesis techniques for FPGA designs (FPGA-HLS) are much focused on such as in image processing an... [more] | VLD2015-127 pp.93-98 |
| VLD | 2016-03-01 15:35 |
Okinawa | Okinawa Seinen Kaikan | The System Performance Evaluation and the FPGA Top-down Design with High-level Design Koki Murano, Koji Miyanohana, Tetsuya Takeo, Tsutomu Motohama, Noriyuki Minegishi (Mitsubishi Elec.) |
[more] | |
| VLD | 2016-03-01 16:15 |
Okinawa | Okinawa Seinen Kaikan | Noise reduction effect for input dependence of Zigzag Power Gating Tadahiro Kanamoto, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2015-128 |
In Power Gating techniques to reduce leakage current, there is the technology called Zigzag Power Gating. Zigzag Power G... [more] | VLD2015-128 pp.99-103 |
| VLD | 2016-03-01 16:40 |
Okinawa | Okinawa Seinen Kaikan | Optimization technique of substrate voltage for Dynamic Multi-Vth methodology in Silicon-on-thin BOX. Hanano Suzuki, Kimiyoshi Usami (Shibaura IT) VLD2015-129 |
Silicon-on-Thin-BOX is one of the FD-SOI devices. It operates at ultra-low voltage and it is possible to effectively cha... [more] | VLD2015-129 pp.105-110 |
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