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Technical Committee on Dependable Computing (DC) (Searched in: 2014)
Search Results: Keywords 'from:2014-06-20 to:2014-06-20'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| DC | 2014-06-20 13:15 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Development of a delay time measurement circuit by inserting buffers Takuya Yamamoto, Yukiya Miura (Tokyo Metropolitan Univ.)  DC2014-10 |
According to the scaling down, lower power design, and highly operational frequency of the device, the process variabili... [more] | DC2014-10 pp.1-6 |
| DC | 2014-06-20 13:40 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A method of LSI degradation estimation using ring oscillators Tatsunori Ikeda, Yukiya Miura (Tokyo Metropolitan Univ.) DC2014-11 |
Aging called Negative Bias Temperature Instability (NBTI), Negative Bias Temperature Instability (NBTI) and Chanel Hot C... [more] | DC2014-11 pp.7-14 |
| DC | 2014-06-20 14:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A X-Filling Method for Low-Capture-Power Scan Test Generation Fuqiang Li, Xiaoqing Wen, Kohei Miyase, Stefan Holst, Seiji Kajihara (Kyushu Inst. of Tech.) DC2014-12 |
In order to generate a low capture power test pattern, we propose an X-filling method to suppress local switching activ... [more] |
DC2014-12 pp.15-20 |
| DC | 2014-06-20 14:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Capture Power Evaluation for A Low Power BIST Method Using A TEG Chip Toshiya Nishida (Kyushu Inst. of Tech.), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.) DC2014-13 |
Voltage drop by a momentary current change during capture cycles in scan-based testing brings an increase in path delay ... [more] | DC2014-13 pp.21-26 |
| DC | 2014-06-20 15:10 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Fault Tolerant Response Analyzer for Built-in Self-test Yuki Fukazawa (Mie Univ.), Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) DC2014-14 |
Reliable built-in self-test (Reliable BIST) is a scheme in which embedded BIST circuits are designed to be tolerant of t... [more] | DC2014-14 pp.27-32 |
| DC | 2014-06-20 15:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Floating-point Multiplier with Reduced Precision Error Checking by Partial Duplication Nobutaka Kito (Chukyo Univ.), Kazushi Akimoto, Naofumi Takagi (Kyoto Univ.) DC2014-15 |
We propose a floating-point multiplier with reduced precision error checking. The multiplier uses a truncated multiplie... [more] |
DC2014-15 pp.33-38 |
| DC | 2014-06-20 16:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Binding Method for Hierarchical Testability Using Results of Test Environment Generation Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2014-16 |
Hierarchical test generation methods using functional register-transfer level circuits have been proposed as efficient t... [more] | DC2014-16 pp.39-44 |
| DC | 2014-06-20 16:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An evaluation for Testability of Functional k-Time Expansion Models Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2014-17 |
A test generation method using functional k-time expansion models for data paths was proposed. In the test generation m... [more] |
DC2014-17 pp.45-50 |
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