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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CS, CAS | 2020-02-27 11:45 |
Kumamoto | Detecting Resistive-Open Defects of Power TSVs in 3D-ICs Koutaro Hachiya (Teikyo Heisei Univ.), Atsushi Kurokawa (Hirosaki Univ.)  CAS2019-104 CS2019-104 |
A method is proposed which detects resistive-open defects of power TSVs in PDNs by measuring resistance between power mi... [more] | CAS2019-104 CS2019-104 pp.37-41 |
|
| HWS (2nd) |
2018-12-13 16:10 |
Tokyo | Tokyo Univ. Takeda Bldg. Takeda Hall | [Poster Presentation]
Hardware Trojan Attack and Countermeasures in Bundle-Data Asynchronous Circuits Koutaro Inaba, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.) |
(Advance abstract in Japanese is available) [more] | |
| VLD, CAS, MSS, SIP | 2016-06-17 15:10 |
Aomori | Hirosaki Shiritsu Kanko-kan | Clock Distribution Network with Multiple Source Buffers for Stacked Chips Nanako Niioka, Masashi Imai, Kaoru Furumi, Atsushi Kurokawa (Hirosaki Univ.) CAS2016-31 VLD2016-37 SIP2016-65 MSS2016-31 |
In this report, we present a method to reduce clock skew among stacked chips by a clock distribution network with multip... [more] | CAS2016-31 VLD2016-37 SIP2016-65 MSS2016-31 pp.167-172 |
| VLD, CAS, MSS, SIP | 2016-06-17 15:30 |
Aomori | Hirosaki Shiritsu Kanko-kan | Thermal Analysis in 3D ICs Kaoru Furumi, Masashi Imai, Nanako Niioka, Atsushi Kurokawa (Hirosaki Univ.) CAS2016-32 VLD2016-38 SIP2016-66 MSS2016-32 |
Three-dimensional integrated circuits (3D ICs) lead to higher power densities than 2D ICs because of the stacking of mul... [more] | CAS2016-32 VLD2016-38 SIP2016-66 MSS2016-32 pp.173-178 |
| VLD, CAS, MSS, SIP | 2016-06-17 16:10 |
Aomori | Hirosaki Shiritsu Kanko-kan | Tamper Resistant Asynchronous Pipeline Circuits using Random Delay Elements Daiki Toyoshima, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.) CAS2016-34 VLD2016-40 SIP2016-68 MSS2016-34 |
Asynchronous bundled-data transfer circuits use delay elements as a strobe signal which indicates the stable state of th... [more] | CAS2016-34 VLD2016-40 SIP2016-68 MSS2016-34 pp.185-190 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 13:45 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Evaluation of Low-Voltage Characteristics of QDI model based Asynchronous VLSI Ryuhei Tachika, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.) VLD2015-67 DC2015-63 |
In synchronous circuits, it is needed to distribute an identical clock signal to the whole chip with a constant frequenc... [more] | VLD2015-67 DC2015-63 pp.189-194 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 14:10 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Implementation and Evaluation of Peak Current Reduction Bandpass Filter using Asynchronous Circuits Tatsuya Ishikawa, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.) VLD2015-68 DC2015-64 |
In synchronous circuits, peak currents flow at a constant frequency since a global clock signal which is a timing signal... [more] | VLD2015-68 DC2015-64 pp.195-200 |
| DC | 2015-06-16 15:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Study on Function Test of Latch-based Asynchronous Pipeline Circuits Daiki Toyoshima, Kyohei Terayama, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.) DC2015-19 |
Asynchronous MOUSETRAP pipeline circuit is a simple and fast circuit thanks to the 2-phase handshaking protocol which ha... [more] | DC2015-19 pp.19-24 |
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