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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 11:05 |
Kagoshima | [Invited Talk]
Toward VLSI Reliability Enhancement by Reconfigurable Architecture Takao Onoye, Masanori Hashimoto (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Dawood Alnajjar, Hiroaki Konoura (Osaka Univ.)  VLD2013-87 CPM2013-122 ICD2013-99 CPSY2013-63 DC2013-53 RECONF2013-51 |
Owing to wide spread of VLSI systems, a failure of the VLSIs may lead critical issue in our daily life. Especially in so... [more] | VLD2013-87 CPM2013-122 ICD2013-99 CPSY2013-63 DC2013-53 RECONF2013-51 p.183(VLD), p.81(CPM), p.81(ICD), p.27(CPSY), p.183(DC), p.69(RECONF) |
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| RECONF | 2013-05-20 17:40 |
Kochi | Kochi Prefectural Culture Hall | Flexible reliability mixed-grained reconfigurable architecture supporting behavioral synthesis Hiroaki Konoura, Dawood Alnajjar (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. Tech.), Hiroyuki Ochi (Ritsumeikan Univ.), Takashi Imagawa (Kyoto Univ.), Shinichi Noda, Kazutoshi Wakabayashi (NEC), Masanori Hashimoto, Takao Onoye (Osaka Univ.) RECONF2013-8 |
This paper proposes a mixed-grained reconfigurable architecture that supports C-based behavioral synthesis and flexibl... [more] |
RECONF2013-8 pp.41-46 |
| SIP, CAS, CS | 2013-03-14 15:05 |
Yamagata | Keio Univ. Tsuruoka Campus (Yamagata) | A study on electrode configuration for distance estimation based on capacitive coupling between sensor nodes Tatsuya Shinada, Masanori Hashimoto, Takao Onoye (Osaka Univ.) CAS2012-119 SIP2012-150 CS2012-125 |
We are studying a 3D modeling system using a sensor network that distributes many tiny sensor nodes in a exible object l... [more] | CAS2012-119 SIP2012-150 CS2012-125 pp.131-136 |
| VLD | 2013-03-04 14:40 |
Okinawa | Okinawa Seinen Kaikan | Self-Compensation of Manufacturing Variability using On-Chip Sensors Yuma Higuchi, Masanori Hashimoto, Takao Onoye (Osaka Univ.) VLD2012-138 |
Manufacturing variability is becoming more influential on circuit performance and parametric yield, and is predicted to ... [more] | VLD2012-138 pp.13-17 |
| VLD | 2013-03-06 10:30 |
Okinawa | Okinawa Seinen Kaikan | A worst-case-aware design methodology for oscillator-based true random number generator with stochastic behavior modeling Takehiko Amaki, Masanori Hashimoto (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Takao Onoye (Osaka Univ.) VLD2012-154 |
This paper presents a worst-case-aware design methodology for an oscillator-based true random number generator (TRNG) ro... [more] | VLD2012-154 pp.99-104 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 14:30 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | An observational study on fault-avoidance methods using dynamic partial reconfiguration Hiroaki Konoura (Osaka Univ.), Takashi Imagawa (Kyoto Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Masanori Hashimoto, Takao Onoye (Osaka Univ.) RECONF2012-59 |
Fault-avoidance methods using dynamic partial reconfiguration on reconfigurable devices are proposed for avoiding the em... [more] | RECONF2012-59 pp.71-76 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2012-11-28 14:55 |
Fukuoka | Centennial Hall Kyushu University School of Medicine | Neutron Induced Single Event Multiple Transients With Voltage Scaling and Body Biasing Ryo Harada (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Masanori Hashimoto, Takao Onoye (Osaka Univ.) VLD2012-100 DC2012-66 |
This paper presents measurement results of neutron induced single event multiple transients (SEMT). We devise an SEMT me... [more] | VLD2012-100 DC2012-66 pp.237-241 |
| ICD | 2011-12-15 16:10 |
Osaka | [Poster Presentation]
An oscillator-based true random number generator with jitter amplifier Takehiko Amaki, Masanori Hashimoto, Takao Onoye (Osaka Univ.) ICD2011-118 |
This paper presents an oscillator-based TRNG (true random number generator) with jitter amplifier. The proposed jitter a... [more] | ICD2011-118 pp.87-92 |
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| ICD | 2011-12-15 16:10 |
Osaka | [Poster Presentation]
Signal-Dependent Analog-to-Digital Conversion based on MINIMAX Sampling Igors Homjakovs, Masanori Hashimoto (Osaka Univ.), Tetsuya Hirose (Kobe Univ.), Takao Onoye (Osaka Univ.) ICD2011-121 |
This paper presents an architecture of signal-dependent analog-to-digital converter (ADC) based on MINIMAX sampling sche... [more] | ICD2011-121 pp.105-107 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 09:00 |
Miyazaki | NewWelCity Miyazaki | [Invited Talk]
Ultra Low Voltage Subthreshold Circuit Design Masanori Hashimoto (Osaka Univ.) VLD2011-82 DC2011-58 |
Subthreshold circuits, which are drawing attention for ultra low-power applications, are reviewed in terms of power diss... [more] | VLD2011-82 DC2011-58 pp.173-178 |
| RECONF | 2011-05-12 13:55 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Evaluation of reliability enhancement achieved by fault avoidance on dynamically reconfigurable architectures Hiroaki Konoura (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. Tech.), Masanori Hashimoto, Takao Onoye (Osaka Univ.) RECONF2011-6 |
For wear-out failures, some fault avoidance methods on dynamically reconfigurable devices have been discussed. In order... [more] | RECONF2011-6 pp.31-36 |
| ICD | 2010-12-16 15:10 |
Tokyo | RCAST, Univ. of Tokyo | [Poster Presentation]
Evaluation of Power Gating Structures Focusing on Power Supply Noise with Measurement and Simulation Yasumichi Takai, Masanori Hashimoto, Takao Onoye (Osaka Univ.) ICD2010-109 |
This paper investigates the impact of power gating structure on power supply noise using 65nm test chip measurement and ... [more] | ICD2010-109 pp.75-80 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-30 13:15 |
Fukuoka | Kyushu University | [Invited Talk]
Paper Writing Guide for International Conferences
-- Implications in VLSI design methodology field -- Masanori Hashimoto (Osaka Univ.) VLD2010-69 DC2010-36 |
This talk discusses how to write a technical paper that is likely to be accepted for international conferences on the ba... [more] | VLD2010-69 DC2010-36 p.91 |
| VLD | 2010-09-28 15:25 |
Kyoto | Kyoto Institute of Technology | Measurement Circuits for Acquiring SET PulseWidth Distribution with Fine Time Resolution Ryo Harada, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye (Osaka Univ.) VLD2010-55 |
This paper presents two circuits to measure pulse width distribution of single event transients (SETs). We first revie... [more] |
VLD2010-55 pp.77-82 |
| VLD | 2009-03-13 10:40 |
Okinawa | Layout Aware Cell Clustering for Body Biasing Koichi Hamamoto (Osaka Univ.), Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye (Osaka Univ./JST-CREST) VLD2008-159 |
Body bias control has been widely studied for performance compensation. In order to reduce leakage increase involved by ... [more] | VLD2008-159 pp.195-200 |
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| VLD | 2009-03-13 11:05 |
Okinawa | Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in Subthreshold Circuits Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye (Osaka Univ./JST-CREST) VLD2008-160 |
This paper presents modeling of manufacturing variability and body bias effect for subthreshold circuits based on mea... [more] |
VLD2008-160 pp.201-206 |
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| VLD | 2009-03-13 11:30 |
Okinawa | Decoupling Capacitance Allocation for Timing with Statistical Noise Model and Timing Analysis Takashi Enami, Masanori Hashimoto (Osaka Univ.), Takashi Sato (Tokyo Inst. of Tech.) VLD2008-161 |
This paper presents an allocation method of decoupling capacitance that explicitly considers timing. We have found and ... [more] |
VLD2008-161 pp.207-212 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 15:40 |
Fukuoka | Kitakyushu Science and Research Park | Coarse-Grained Reconfigurable Architecture with Flexible Reliability Younghun Ko, Dawood Alnajjar, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye (Osaka Univ.) VLD2008-73 DC2008-41 |
Acceptable soft error rate on a VLSI chip varies depending on applications and operating environment so that recent VLSI... [more] | VLD2008-73 DC2008-41 pp.79-84 |
| VLD, CAS, SIP | 2008-06-26 15:05 |
Hokkaido | Hokkaido Univ. | An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye (Osaka Univ.) CAS2008-14 VLD2008-27 SIP2008-48 |
Body-biasing is expected to be a common design technique, then area efficient implementation in layout has been demanded... [more] | CAS2008-14 VLD2008-27 SIP2008-48 pp.75-79 |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB | 2008-03-28 09:30 |
Kagoshima | On Evaluation Methods of nMOS Level Shifter Circuits Makoto Otsu, Shingo Takahashi, Shuji Tsukiyama (Chuo Univ.), Masanori Hashimoto (Osaka Univ.), Isao Shirakawa (Univ. of Hyogo) DC2007-104 CPSY2007-100 |
When the process technology or required specification is changed, we face a problem of finding the optimum circuit among... [more] | DC2007-104 CPSY2007-100 pp.121-126 |
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