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Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-29
13:45		 Kagoshima   A 3-D NoC architecture using CSMA/CD bus for inter-chip wireless communication
Takahiro Kagami, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) CPSY2013-72		 Wireless 3-D chip multiprocessors(CMPs), in which inductors with CMOS-based transceivers are used for an inter-chip wire... [more] CPSY2013-72
pp.77-82
SANE, SAT
(Joint)		 2011-02-24
15:30		 Hyogo NICT Kobe Research Laboratories High-speed 3-dimensional Target Reconstruction Algorithm with RPM Method Extended to Rotating Target Model
Hiroyuki Yamada, Shouhei Kidera, Tetsuo Kirimoto (UEC) SANE2010-161		 A 3-dimensional reconstruction algorithm based on a layover appeared in ISAR image has been proposed , which is suitable... [more] SANE2010-161
pp.13-18
ED, SDM 2010-07-02
16:05		 Tokyo Tokyo Inst. of Tech. Ookayama Campus The optimum physical targets of the 3-dimensional vertical FG NAND flash memory cell arrays with the extended sidewall control gate (ESCG) structure
Moon-Sik Seo (Tohoku Univ.), Tetsuo Endoh (Tohoku Univ./JST) ED2010-101 SDM2010-102		 Recently, the 3-dimensional vertical Floating Gate (FG) NAND flash memory cell arrays with the extended sidewall control... [more] ED2010-101 SDM2010-102
pp.225-230
US 2009-06-26
14:15		 Chiba   3-D Sound field simulation using GPU
Takao Tsuchiya, Atsushi Morikouchi, Masahiro Otsuka (Doshisha Univ.) US2009-16		 In this paper, a multi-GPU (Graphic Processing Unit) system is applied
to a high-performance numerical simulation of t... [more]		 US2009-16
pp.17-20
SDM, VLD 2006-09-26
13:00		 Tokyo Kikai-Shinko-Kaikan Bldg. Improvement of Drive Current in Bulk-FinFET using Full 3D Process/Device Simulations
Takahisa Kanemura, Takashi Izumida, Nobutoshi Aoki, Masaki Kondo, Sanae Ito, Toshiyuki Enda, Kimitoshi Okano, Hirohisa Kawasaki, Atsushi Yagishita, Akio Kaneko, Satoshi Inaba, Mitsutoshi Nakamura, Kazunari Ishimaru, Kyoichi Suguro, Kazuhiro Eguchi (Toshiba Corp.) 		We discussed the optimization of structure of bulk-FinFETs and ion implantations by using 3-D process and device simulat... [more] VLD2006-43 SDM2006-164
pp.25-29
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