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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] | 2015-03-07 13:25 |
Kagoshima | Design and Evaluation of a Floating-point Multiplier with Online Error Detection by Partial Duplication Nobutaka Kito (Chukyo Univ.), Kazushi Akimoto, Naofumi Takagi (Kyoto Univ.)  CPSY2014-181 DC2014-107 |
A floating-point multiplier with reduced precision error detection is proposed. It uses a truncated multiplier for chec... [more] |
CPSY2014-181 DC2014-107 pp.125-130 |
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| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 16:40 |
Oita | B-ConPlaza | A complex multiplier using two floating-point fused multiply-add unit Yuhei Takata, Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.) CPSY2014-76 |
Complex operations are used in scientific computing and signal processing. Floating-point complex multiplication is imp... [more] |
CPSY2014-76 pp.25-29 |
| DC | 2014-06-20 15:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Floating-point Multiplier with Reduced Precision Error Checking by Partial Duplication Nobutaka Kito (Chukyo Univ.), Kazushi Akimoto, Naofumi Takagi (Kyoto Univ.) DC2014-15 |
We propose a floating-point multiplier with reduced precision error checking. The multiplier uses a truncated multiplie... [more] |
DC2014-15 pp.33-38 |
| SCE | 2012-07-19 11:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Design of a 2bit Bit-Slice Half-Precision Floating-Point Multiplier Using SFQ Circuits Yohei Naruse (Kyoto Univ.), Nobutaka Kito (Chukyo Univ.), Naofumi Takagi (Kyoto Univ.) SCE2012-12 |
Single flux quantum (SFQ) circuits are expected as next-generation circuits. Arithmetic circuits using SFQ circuits ha... [more] |
SCE2012-12 pp.19-23 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 09:00 |
Miyazaki | NewWelCity Miyazaki | A Circuit Partitioning Strategy for 3-D Integrated Floating-point Multipliers Kazushige Kawai, Jubee Tada (Yamagata Univ.), Ryusuke Egawa, Hiroaki Kobayashi (Tohoku Univ.), Gensuke Goto (Yamagata Univ.) CPM2011-162 ICD2011-94 |
Three-dimensional (3-D) integration technologies are attractive for enhancing the speed of the arithmetic circuits. To i... [more] | CPM2011-162 ICD2011-94 pp.67-72 |
| SCE | 2010-07-22 14:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | 50 GHz Tests of SFQ Floating-Point Multipliers Using 10 kA/cm2 Nb Advanced Process Yasuhiro Shimamura, Toshiki Kainuma, Fumishige Miyaoka, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.), Akira Fujimaki, Kazuyoshi Takagi (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) SCE2010-22 |
We have been developing a large-scale reconfigurable data-path (LSRDP) using single-flux-quantum (SFQ) circuit to realiz... [more] | SCE2010-22 pp.47-52 |
| SCE | 2009-10-20 13:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Design of SFQ Floating-Point Units Using Nb Advanced Process Toshiki Kainuma, Yasuhiro Shimamura, Fumishige Miyaoka, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama Nat. Univ.), Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi (Nagoya Univ.) SCE2009-19 |
We are developing a large-scale reconfigurable data-path (LSRDP) based on the single-flux-quantum (SFQ) circuits, which ... [more] | SCE2009-19 pp.13-18 |
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